S1D15605D11B Epson Company, S1D15605D11B Datasheet - Page 76
S1D15605D11B
Manufacturer Part Number
S1D15605D11B
Description
Single-chip dot matrix liquid crystal display drivers
Manufacturer
Epson Company
Datasheet
1.S1D15605D11B.pdf
(87 pages)
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S1D15605 Series
*1
*2
*3
*4
*5
8–74
Address hold time
Address setup time
System cycle time
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
Data setup time
Address hold time
RD access time
Output disable time
Address hold time
Address setup time
System cycle time
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
Data setup time
Address hold time
RD access time
Output disable time
This is in the case of making the access by WR and RD,setting the CS1=LOW.
This is the case of making the accese by CS1,setting the WR,RD=LOW.
The rise and fall times (
All timings are specified based on the 20 and 80% of V
t
system cycle time at high speed, they are specified for (
WR,RD are at the LOW level.
CCLW
Item
Item
and
t
CCLR
are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and
t
r
and
D0 to D7
D0 to D7
Signal
Signal
WR
WR
WR
WR
RD
RD
RD
RD
A0
A0
A0
A0
t
f
) of the input signal are specified for less than 15 ns.When using the
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AH8
AW8
CYC8
CCLW
CCLR
CCHW
CCHR
DS8
DH8
ACC8
OH8
AH8
AW8
CYC8
CCLW
CCLR
CCHW
CCHR
DS8
DH8
ACC8
OH8
Table 27
Table 28
EPSON
CL = 100 pF
CL = 100 pF
Condition
Condition
DD
t
r
.
+
(V
t
(V
f
)
DD
DD
(
t
= 2.7 V to 4.5 V, Ta = –40 to 85 C )
= 1.8 V to 2.7 V, Ta = –40 to 85 C )
CYC8
-
t
1000
Min.
Min.
CCLR
300
120
120
240
120
120
60
60
60
40
15
10
80
30
10
—
—
0
0
0
0
Rating
Rating
-
t
CCHR
Max.
Max.
140
100
280
200
).
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Rev. 2.4a
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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