L6000 ST Microelectronics, Inc., L6000 Datasheet - Page 16

• Manufacturer Part Number: L6000
• Description: Single Chip Read & Write Channel
• Manufacturer: ST Microelectronics, Inc.

L6000
The internal register map for the serial port is shown below:
The bit map of each register (except CA, CB & PD) is as follows:
asserted, then the SERIAL CLOCK+ is driven
with the positive edge latching the state of SE-
RIAL DATA. The actual data is latched into each
register in the L6000 when SERIAL ENABLE is
disasserted, so this signal MUST be driven low
16/24
Bit
LSB
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
2
3
4
5
6
7
FCutoff register
FBoost register
DVTH register
SVTH register
PSN register
PSM register
VCO CENT register
WIN SHIFT register
WRT PREC register
where:
1
1
1
1
1
1
1
1
1
0
0
0
0
Address Bits
Symbol
2
0
0
0
0
0
0
1
1
1
1
1
1
EPDT
FDCT
BYPT
UT
DT
PD
ET
3
0
0
1
1
0
1
0
1
0
0
1
1
4
0
0
0
0
1
1
0
0
0
0
0
0
Control register CA:
5
0
0
0
0
0
0
0
0
0
0
0
0
MSB
Function
Enable Phase Detector (frequency
synthesizer)
Pump Up (FLTR1 sources current,
FLTR1 sinks current) Test mode
Pump Down (FLTR1 sinks current,
FLTR1 sources current) Test Mode
Enable frequency synthesizer Circuit
Function
Bypass frequency synthesizer Circuit
Function
TEST Enable Pulse Detector Test
Points, COUT and DOUT
Force AGC Charge Pump into Fast
Decay Mode
Unused
6
0
0
0
0
0
0
0
0
0
0
0
0
X = Unused bit or don’t care bit
DEDC = Enable dual comparator qualifier in Data read mode.
SEDC = Enable dual comparator qualifier in Servo read mode.
FSC = The frequency synthesizer back comparator state
TDAC1 = DAC Testing control bit #1
TDAC0 = DAC Testing control bit #0
TDAC1
Blk Diagr.
DEDC
SEDC
Address
FSC
M7
X
X
X
X
R0B
R0A
R1A
R0E
R0D
R0C
R02
R03
R12
R06
R04
R05
TDAC0
WRT PREC
VCO CENT
WIN SHIFT
DR6
FC6
FB6
VD6
VS6
M6
Symbol
N6
FCutoff
FBoost
PSMM
X
PSNN
DVTH
SVTH
PD
CA
CB
WSE
FC5
VD5
VS5
DR5
FB5
M5
N5
Power Down Mode Control
DACF-Filter cutoff Frequency Control
DACS-Filter Boost Control
Pulse Detector Voltage Threshold Control (Data Read Mode)
Pulse Detector Voltage Threshold Control (Servo Read Mode)
Control A (Pulse Detector, Filter, frequency synthesizer Control)
Counter Value (frequency synthesizer)
Counter Value (frequency synthesizer)
VCO Center Frequency
Window Shift Magnitude,Direction
Write Precomp magnitude
Control B (Data Separator, Endec Control)
X
Bit
0
1
2
3
4
5
6
7
after EACH register write; failure to deassert SE-
RIAL ENABLE before a 17th SERIAL CLOCK+
will erase ( invalidate ) the previous 16 clock cy-
cles. This also precludes SERIAL CLOCK+ from
being a free running clock in the system. The
WSD
VD4
DR4
FC4
FB4
VS4
M4
N4
READ DATA I/O Pin Input Control
X
Symbol
EPDD
SOFT
DW
GS
UD
DD
ED
WS3
WP3
VD3
DR3
FC3
FB3
VS3
M3
N3
Control register CB:
Function
Function
Direct Write (Bypass Endec)
Enable Phase Detector Gain
Switching
Enable Phase Detector (Data
Separator)
Pump Up (FLTR2 sources current,
FLTR2 sinks current) Test mode
Pump Down (FLTR sinks current,
FLTR2 sources current) Test mode
Enable Data Separator Test Point
Outputs
Select Soft or Hard Sector Operation
WS2
WP2
DR2
FC2
FB2
VD2
VS2
M2
N2
WP1
WS1
DR1
FC1
VD1
VS1
FB1
M1
N1
WS0
WP0
VD0
DR0
FC0
VS0
FB0
M0
N0