L6000 ST Microelectronics, Inc., L6000 Datasheet - Page 5

• Manufacturer Part Number: L6000
• Description: Single Chip Read & Write Channel
• Manufacturer: ST Microelectronics, Inc.

PIN DESCRIPTION (continued)
OUTPUT
64, 63
56, 55
58, 57
Pin #
29
46
28
25
21
27
24
20
13
READ REF CLOCK
ADDR MARK DET
FILT NORM OUT,
FILT NORM OUT
READ DATA I/O
POSITION OUT
FILT DIFF OUT,
FILT DIFF OUT
FREQ OUT TP
WRITE DATA
READ NRZ
AGC OUT,
MULT TP1
MULT TP2
AGC OUT
OUTPUT
Symbol
Type
I/O
O
O
O
O
O
O
O
O
O
O
0
AGC AMPLIFIER OUTPUT: Differential AGC amplifier output pins.
READ DATA I/O: Bi-directional TTL pin. Output is active in the servo mode or
when both READ GATE and WRITE GATE are deasserted. In test mode, this
is a TTL input used to drive the data separator. The TTL input is enabled by
setting RDI in the control register CB.
POSITION ERROR SIGNAL: A Position error signal of A minus B output which
is referenced to SERVO REF V.
FILTER DIFFERENTIAL NORMAL OUTPUTS: Low pass & boosted filter
output signals. Must be AC coupled to the next stage nominally DATA PATH.
FILTER DIFFERENTIAL DIFFERENTIADED OUTPUTS: Differentiated filter
outputs should be AC coupled to the next stage nominally CLOCK PATH.
ADDRESS MARK DETECT: Tristate output pin with TTL output levels. It is in
its high impedance state when WRITE GATE is asserted. When READ GATE
is asserted and the register bit is set for soft sector, an address mark search is
initiated in the soft sector operation. This output is latched low (true) when an
address mark has been detected. Deasserting pin READ GATE deasserts pin
ADDR MARK DET.
MULTIPLEXED TEST POINT OUTPUT: An open emitter ECL output test point.
The test point output is enabled by Setting ED in the control registerCB. The
controlling signal is PD_TEST in the control register CA. When PD_TEST is low ,
the test point output is the delayed read data DRD. The posistive edges of this
signal indicate the data bit position. The positive edges of the DRD and VCOREF
outputs can be used to estimate window centering. The time jitter of DRD’s
positive edge is an indication of media bit jitter. When PD_TEST is high the test
point out is the comparator of the pulse qualifier. The positive edge indicates that
the input signal has exceeded the positive threshold while a negative edge
indicates that the input signal has gone below the negative threshold. Two external
resistors are required to use this pin. They should be removed during normal
operation to reduce power dissipation.
NRZ OUTPUT DATA: Tristate ouput pin with TTL output levels. It is in its high
impedance state when READ GATE is deasserted. Read data output when
READ GATE is asserted.
READ REFERENCE CLOCK: TTL output. A multiplexed clock source used by
the controller, see Clocks and Modes. During a mode change, no glitches are
generated and no more than one lost clock pulse will occur. READ REF
CLOCK remains Fout/3 after READ GATE is asserted, until after synchronized
bits are detected.
MULTIPLEXED TEST POINT OUTPUT: An open emitter ECL output test point.
This test point output is enabled by using the same control bit enabling the
MULT TP1 output. When the controlling signal, PD_TEST is desserted, the test
point output is the VCO reference input (VCOREF) to the phase detector. The
positive edges are phase locked to Delayed Read Data (DRD). The negative
edges of this open emitter output signal indicate the edges of the decode
window. When PD_TEST is high, the test point output represents the state of
the clock comparator in the pulse qualifier. The signal transitions indicate zero
crossing of the differentiated signal from the electronic filter. Two external
resistor are required to use this pin. They should be removed during normal
operation to reduce power dissipation.
WRITE DATA: TTL output. Encoded write data output. The data is
automatically resynchronized (independent of the delay between READ REF
CLOCK and WRITE CLOCK) to the reference clock FSout. Falling edge of the
WRITE DATA is the data edge.
REFERENCE FREQUENCY OUTPUT: An open emitter ECL output test point.
The frequency is the frequency synthesizer output frequency. This output is
enabled by control register CA. Two external resistors are required to use this
pin. They should be removed during normal operation to reduce power
dissipation.
Description
L6000
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