ADP3160 Analog Devices, ADP3160 Datasheet - Page 7

• Manufacturer Part Number: ADP3160
• Description: 5-Bit Programmable 2-Phase Synchronous Buck Controller
• Manufacturer: Analog Devices

Active Current Sharing
The ADP3160 and ADP3167 ensure current balance in the two
phases by actively sensing the current through a single sense resistor.
During one phase’s ON time, the current through the respective
high-side MOSFET and inductor is measured through the sense
resistor (R4 in Figure 6). When the comparator (CMP1 in the
Functional Block Diagram) threshold programmed by the g
fier is reached, the high-side MOSFET turns off. In the next cycle,
the device switches to the second phase. The current is measured
with the same sense resistor and the same internal comparator,
ensuring accurate matching. This scheme is immune to imbalances
in the MOSFETs’ R
If for some reason one of the phases fails, the other phase will
still be limited to its maximum output current (one-half of the
short circuit current limit). If this is not sufficient to supply the
load, the output voltage will droop and cause the PWRGD
output to signal that the output voltage has fallen out of its
specified range.
Short Circuit Protection
The ADP3160 and ADP3167 have multiple levels of short
circuit protection to ensure fail-safe operation. The sense resis-
tor and the maximum current sense threshold voltage given in
the specifications set the peak current limit.
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
REV. B
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Table I. Output Voltage vs. VID Code
VID2 VID1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
DS(ON)
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
and inductors’ parasitic resistances.
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
V
No CPU
1.100 V
1.125 V
1.150 V
1.175 V
1.200 V
1.225 V
1.250 V
1.275 V
1.300 V
1.325 V
1.350 V
1.375 V
1.400 V
1.425 V
1.450 V
1.475 V
1.500 V
1.525 V
1.550 V
1.575 V
1.600 V
1.625 V
1.650 V
1.675 V
1.700 V
1.725 V
1.750 V
1.775 V
1.800 V
1.825 V
1.850 V
OUT(NOM)
m
ampli-
–7–
When the load current exceeds the current limit, the excess current
discharges the output capacitor. When the output voltage is
below the foldback threshold V
output current is cut by reducing the current sense threshold
from the current limit threshold, V
old, V
oscillator frequency is reduced by a factor of 5 when the output is
0 V. This further reduces the average current in short circuit.
Power Good Monitoring
The Power Good comparator monitors the output voltage of the
supply via the FB pin. The PWRGD pin is an open-drain output
whose high level (when connected to a pull-up resistor) indicates
that the output voltage is within the specified range of the nomi-
nal output voltage requested by the VID DAC. PWRGD will go
low if the output is outside this range.
Output Crowbar
The ADP3160 and ADP3167 include a crowbar comparator that
senses when the output voltage rises higher than the specified trip
threshold, V
and sets both PWM outputs low. The driver ICs turn off the
high-side MOSFETs and turn on the low-side MOSFETs, thus
pulling the output down as the reversed current builds up in the
inductors. If the output overvoltage is due to a short of the high-
side MOSFET, this action will current limit the input supply or
blow its fuse, protecting the microprocessor from destruction.
The crowbar comparator releases when the output drops below the
specified reset threshold, and the controller returns to normal
operation if the cause of the overvoltage failure does not persist.
Output Disable
The ADP3160 and ADP3167 include an output disable function
that turns off the control loop to bring the output voltage to 0 V.
Because an extra pin is not available, the disable feature is accom-
plished by pulling the COMP pin to ground. When the COMP pin
drops below 0.56 V for the ADP3160 and 0.64 V for the ADP3167,
the oscillator stops and both PWM signals are driven low. This
function does not place the part in a low quiescent current shut-
down state, and the reference voltage is still available. The COMP
pin should be pulled down with an open collector or open-drain
type of output capable of sinking at least 2 mA.
APPLICATION INFORMATION
A VRM 9.0-Compliant Design Example
The design parameters for a typical high-performance Intel CPU
application (see Figure 6) are as follows:
Input Voltage (V
Nominal Output Voltage (V
Static Output Tolerance (V ) = (V+) – (V–) =
0 mV – (–130 mV) = 130 mV
Maximum Output Current (I
Output Current di/di < 50 A/ s
Average Output Tolerance (V
V
CS(FOLD)
OUT
+
CROWBAR
(V+) + (V–)
. Along with the resulting current foldback, the
2
. This comparator overrides the control loop
IN
) = 12 V
ADP3160/ADP3167
=
FB(LOW)
1 635
OUT
CS(CL)
.
O
) = 53.4 A
) = 1.7 V
AVG
, the maximum deliverable
V
, to the foldback thresh-
)
=