AAT2601 Analogic Corporation, AAT2601 Datasheet - Page 32

• Manufacturer Part Number: AAT2601
• Manufacturer: Analogic Corporation

32
Table 8: SYS Bit Setting for SYSOUT Power Path.
SYS Bit
LDO1
LDO2
LDO3
LDO4
LDO5
Timer
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
the Charger Watchdog Timer.
Table 6: Timer Bit Setting for
If USE_USB = L, SYSOUT powered from CHGIN
Table 7: LDO Bit Setting for
LDO Output Voltage Level.
If USE_USB = H, SYSOUT powered from BAT
LDO1
LDO2
LDO3
LDO4
LDO5
SYSOUT always powered from BAT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SYSOUT Power Source
Charger Watchdog Timer
0
0
0
0
0
OFF (and reset to zero)
LDO1 Output Voltage
LDO2 Output Voltage
LDO3 Output Voltage
LDO4 Output Voltage
LDO5 Output Voltage
ON (default)
3.00V (default)
3.00V (default)
3.00V (default)
3.00V (default)
3.00V (default)
2.90V
2.85V
2.80V
2.90V
2.85V
2.80V
2.90V
2.85V
2.80V
2.90V
2.85V
2.80V
2.90V
2.85V
2.80V
w w w . a n a l o g i c t e c h . c o m
Total Power Solution for Portable Applications
Layout Guidance
Figure 10 is the schematic for the evaluation board. The
evaluation board has extra components for easy evalua-
tion; the actual BOM need for a system is shown in Table
9. When laying out the PC board, the following layout
guideline should be followed to ensure proper operation
of the AAT2601:
1. The exposed pad EP must be reliably soldered to
2. The power traces, including GND traces, the LX
3. The input capacitors (C1 and C2) should be con-
4. Keep the switching node LX away from the sensitive
5. The feedback trace for the OUTBUCK pin should be
6. The output capacitor C4 and L1 should be connected
7. The resistance of the trace from the load return to
PGND/AGND and multilayer GND. The exposed ther-
mal pad should be connected to board ground plane
and pins 2 and 16. The ground plane should include
a large exposed copper pad under the package with
VIAs to all board layers for thermal dissipation.
traces and the VIN trace should be kept short, direct
and wide to allow large current flow. The L1 connec-
tion to the LX pins should be as short as possible.
Use several via pads when routing between layers.
nected as close as possible to CHGIN (Pin 28) and
PGND (Pin 2) to get good power filtering.
OUTBUCK feedback node.
separate from any power trace and connected as
closely as possible to the load point. Sensing along a
high current load trace will degrade DC load regula-
tion.
as close as possible and there should not be any
signal lines under the inductor.
the PGND (Pin 2) should be kept to a minimum. This
will help to minimize any error in DC regulation due
to differences in the potential of the internal signal
ground and the power ground.
PRODUCT DATASHEET
AAT2601178
2601.2008.01.1.0