AD9248-20PCB Analog Devices, AD9248-20PCB Datasheet

AD9248-20PCB

Manufacturer Part Number

AD9248-20PCB

Description

14-Bit/ 20/40/65 MSPS Dual A/ D Converter

Manufacturer

Analog Devices

Datasheet

1.AD9248-20PCB.pdf (23 pages)

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FEATURES

Integrated Dual 14-Bit A-to-D Converters

Single 3 V Supply Operation (2.7 V to 3.6 V)

SNR = 73 dBc (to Nyquist, AD9248-65)

SFDR = 83 dBc (to Nyquist, AD9248-65)

Low Power: 600 mW at 65 MSPS

Differential Input with 500 MHz 3 dB Bandwidth

Exceptional Cross Talk Immunity > 85dB

Flexible Analog Input: 1 V p-p to 2 V p-p Range

Offset Binary or Twos Complement Data Format

Clock Duty Cycle Stabilizer

APPLICATIONS

Ultrasound Equipment

IF Sampling in Communications Receivers:

IS-95, CDMA One, IMT-2000

Battery-Powered Instruments

Hand-Held Scopemeters

Low Cost Digital Oscilloscopes

GENERAL DESCRIPTION

The AD9248 is a dual, 3 V, 14-bit, 20/40/65 MSPS analog-to-

digital converter. It features dual high performance sample-and

hold amplifiers and an integrated voltage reference. The

AD9248 uses a multistage differential pipelined architecture

with output error correction logic to provide 14-bit accuracy

and guarantee no missing codes over the full operating

temperature range at up to 65 MSPS data rates. The wide

bandwidth, differential SHA allows for a variety of user

selectable input ranges and offsets including single-ended

applications. It is suitable for various applications including

multiplexed systems that switch full-scale voltage levels in

successive channels and for sampling inputs at frequencies well

beyond the Nyquist rate.

Dual single-ended clock inputs are used to control all internal

conversion cycles. A duty cycle stabilizer is available on the

AD9248-65 and can compensate for wide variations in the

clock duty cycle, allowing the converters to maintain excellent

performance. The digital output data is presented in either

straight binary or twos complement format. Out-of-range

signals indicate an overflow condition, which can be used with

the most significant bit to determine low or high overflow.

Fabricated on an advanced CMOS process, the AD9248 is

available in a space saving 64-lead LQFP and is specified over

the industrial temperature range (–40? C to +85? C).

Rev. PrE

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its use,

nor for any infringements of patents or other rights of third parties that may

result from its use. Specifications subject to change without notice. No license

is granted by implication or otherwise under any patent or patent rights of

Analog Devices. Trademarks and registered trademarks are the property of

their respective companies.

Preliminary Technical Data

6/29/2004

PRODUCT HIGHLIGHTS

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,

U.S.A.

Tel: 781.329.4700

14-Bit, 20/40/65 MSPS

REFB_A

REFT_A

REFT_B

REFB_B

VIN+_A

VIN- _A

SENSE

VIN+_B

AGND

VIN-_B

VREF

Dual A/ D Converter

Pin compatible with AD9238, 12-bit 20/40/65MSPS

ADC.

Speed grade options of 20 MSPS, 40 MSPS, and 65

MSPS allow flexibility between power, cost, and

performance to suit an application.

Low power consumption:

AD9248-65: 65 MSPS = 600 mW.

AD9248-40: 40 MSPS = 330 mW.

AD9248-20: 20 MSPS = 180 mW.

The patented SHA input maintains excellent

performance for input frequencies up to 100 MHz and

can be configured for single-ended or differential

operation.

Typical channel isolation of 85 dB @ f

The clock duty cycle stabilizer (AD9248-65 only)

maintains performance over a wide range of clock

duty cycles.

The OTR output bits indicate when either input signal

is beyond the selected input range.

Multiplexed data output option enables single-port

operation from either data port A or data port B.

AD9248

Figure 1. Functional Block Diagram

0.5V

SHA

DRVDD

AVDD

ADC

DRGND

AGND

Duty Cycle

AD9248

Stabilizer

Control

Clock

Mode

www.analog.com

= 10 MHz.

OTR_B

OTR_A

OEB_B

D13

OEB_A

MUX_SELECT

CLK_A

CLK_B

DCS

SHARED_REF

PWDN_A

PWDN_B

DFS

D13

-D

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