AD9500 Analog Devices, AD9500 Datasheet
AD9500
Manufacturer Part Number
AD9500
Description
Digitally Programmable Delay Generator
Manufacturer
Analog Devices
Datasheet
1.AD9500.pdf
(11 pages)
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a
GENERAL DESCRIPTION
The AD9500 is a digitally programmable delay generator, which
provides programmed delays, selected through an 8-bit digital
code, in resolutions as small as 10 ps. The AD9500 is con-
structed in a high performance bipolar process, designed to
provide high speed operation for both digital and analog circuits.
The AD9500 employs differential TRIGGER and RESET
inputs which are designed primarily for ECL signal levels but
function with analog and TTL input levels. An onboard ECL
reference midpoint allows both of the inputs to be driven by
either single ended or differential ECL circuits. The AD9500
output is a complementary ECL stage, which also provides a
parallel output circuit to facilitate reset timing implementations.
The digital control data is passed to the AD9500 through a
transparent latch controlled by the LATCH ENABLE signal. In
the transparent mode, the internal DAC of the AD9500 will
attempt to follow changes at the inputs. The LATCH ENABLE
is otherwise used to strobe the digital data into the AD9500
latches.
The AD9500 is available as an industrial temperature range
device, –25 C to +85 C, and as an extended temperature range
device, –55 C to +125 C. Both grades are packaged in a 24-lead
cerdip (0.3" package width), as well as 28-leaded and leadless
surface mount packages. The AD9500 is available in versions
compliant with MIL-STD-883. Refer to the Analog Devices
Military Products Databook or current AD9500/883B data
sheet for detailed specifications.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
10 ps Delay Resolution
2.5 ns to 10 s Full-Scale Range
Fully Differential Inputs
Separate Trigger and Reset Inputs
Low Power Dissipation—310 mW
MIL-STD-883 Compliant Versions Available
APPLICATIONS
ATE
Pulse Deskewing
Arbitrary Waveform Generators
High Stability Timing Source
Multiple Phase Clock Generators
Q
R
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
TRIGGER
TRIGGER
ECL
R
RESET
RESET
SET
OFFSET ADJUST
REF
–V
R
S
S
OFFSET ADJUST
TRIGGER
D
–V
7
ECL
DIFFERENTIAL
(MSB)
REFERENCE
REFERENCE
S
CURRENT
FUNCTIONAL BLOCK DIAGRAM
VOLTAGE
ANALOG
TRIGGER
TRIGGER
+V
D
REF
NC
STAGE
C
INPUT
7
ECL
ECL
RESET
RESET
S
S
(MSB)
Digitally Programmable
GROUND
10
11
+V
5
6
7
8
9
REF
C
PIN CONFIGURATIONS
D
D
D
S
S
4
5
6
World Wide Web Site: http://www.analog.com
10
11
12
12
1
2
3
4
5
6
7
8
9
4
(LSB)
13
3
D
0
(Not to Scale)
+V
AD9500
(Not to Scale)
TOP VIEW
AD9500
14 15
D
2
TOP VIEW
S
1
Delay Generator
CONTROL
INTERNAL DAC
D
TTL LATCHES
1
CIRCUIT
TIMING
2
C
D
16
28 27 26
EXT
3
D
17 18
© Analog Devices, Inc., 1999
4
C
24
23
22
20
19
18
17
16
15
14
13
D
21
NC = NO CONNECT
S
5
AD9500
D
D
D
D
D
LATCH ENABLE
R
–V
ECL COMMON
Q
Q
GROUND
Q
AD9500
6
3
2
1
0
S
(MSB)
R
S
(LSB)
D
19
25
24
23
22
21
20
7
D
LATCH ENABLE
GROUND
NC
R
–V
ECL COMMON
ENABLE
ECL COMMON
0
S
LATCH
S
(LSB)
OFFSET
ADJUST
Q
Q
Q
R
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