AD9516-1 Analog Devices, AD9516-1 Datasheet - Page 77

• Manufacturer Part Number: AD9516-1
• Description: 14-Output Clock Generator
• Manufacturer: Analog Devices

Reg.
Addr
(Hex) Bit(s) Name
1E0
1E1
1E1
1E1
1E1
1E1
Reg.
Addr
(Hex) Bit(s)
1A1
1A1
1A1
1A1
1A1
1A1
1A2
Table 59. VCO Divider and CLK Input
<2:0> VCO Divider
<4>
<3>
<2>
<1>
<0>
<5>
<4>
<3>
<2>
<1>
<0>
<0>
Power-Down Clock Input Section Power down the clock input section (including CLK buffer, VCO divider, and CLK tree).
Power-Down VCO Clock Interface Power down the interface block between VCO and clock distribution.
Power-Down VCO and CLK
Select VCO or CLK
Bypass VCO Divider
Name
Bypass Divider 4.2
Bypass Divider 4.1
Divider 4 Nosync
Divider 4 Force High
Start High Divider 4.2
Start High Divider 4.1
Divider 4 DCCOFF
Description
Bypass (and power-down) 4.2 divider logic, route clock to 4.2 output.
<5> = 0; do not bypass.
<5> = 1; bypass.
Bypass (and power-down) 4.1 divider logic, route clock to 4.1 output.
<4> = 0; do not bypass.
<4> = 1; bypass.
Nosync.
<3> = 0; obey chip-level SYNC signal.
<3> = 1; ignore chip-level SYNC signal.
Force Divider 4 output high. Requires that nosync also be set.
<2> = 0; force low.
<2> = 1; force high.
Divider 4.2 start high/low.
<1> = 0; start low.
<1> = 1; start high.
Divider 4.1 start high/low.
<0> = 0; s tart low.
<0> = 1; start high.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
Description
<2>
0
0
0
0
1
1
1
1
<4> = 0; normal operation.
<4> = 1; power-down.
<3> = 0; normal operation.
<3> = 1; power-down.
Power down both VCO and CLK input.
<2> = 0; normal operation.
<2> = 1; power-down.
Select either the VCO or the CLK as the input to VCO divider.
<1> = 0; Select external CLK as input to VCO divider.
<1> = 1; Select VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
Bypass or use the VCO divider.
<0> = 0; use VCO divider.
<0> = 1; bypass VCO divider; cannot select VCO as input when this is selected.
Rev. 0 | Page 77 of 84
<1>
0
0
1
1
0
0
1
1
<0>
0
1
0
1
0
1
0
1
Divide
2
3
4
5
6
Output static
Output static
Output static
AD9516-1