AD9631-EB Analog Devices, AD9631-EB Datasheet - Page 17

• Manufacturer Part Number: AD9631-EB
• Description: Ultralow Distortion/ Wide Bandwidth Voltage Feedback Op Amps
• Manufacturer: Analog Devices

Layout Considerations
The specified high speed performance of the AD9631 and
AD9632 requires careful attention to board layout and compo-
nent selection. Proper RF design techniques and low pass para-
sitic component selection are mandatory.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for the supply bypassing (see
Figure 64). One end should be connected to the ground plane
and the other within 1/8 inch of each power pin. An additional
large (0.47 F–10 F) tantalum electrolytic capacitor should be
connected in parallel, though not necessarily so close, to supply
current for fast, large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the in-
verting input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50
nated at each end.
Evaluation Board
An evaluation board for both the AD9631 and AD9632 is avail-
able that has been carefully laid out and tested to demonstrate
that the specified high speed performance of the device can be
realized. For ordering information, please refer to the Ordering
Guide.
The layout of the evaluation board can be used as shown or
serve as a guide for a board layout.
REV. A
Component
R
R
R
R
R
Small Signal
BW (MHz)
F
G
O
S
T
(Nominal)
(Nominal)
–1
274
274
49.9
100
61.9
90
or 75
+1
140
49.9
130
49.9
320
and be properly termi-
AD9631A
Gain
+2
274
274
49.9
100
49.9
90
+10
2 k
221
49.9
100
49.9
10
Table I.
–17–
Figure 65. Inverting and Noninverting Configurations for
Evaluation Boards
+100
2 k
20.5
49.9
100
49.9
1.3
IN
IN
OPTIONAL
R
+V
–V
–1
274
274
100
100
61.9
250
T
R
S
S
Noninverting Configuration
T
R
R
Inverting Configuration
G
G
R
S
R
Supply Bypassing
S
C1
1000pF
C2
1000pF
+2
274
274
100
100
49.9
250
+V
–V
–V
+V
R
R
F
S
F
S
S
S
AD9631/AD9632
C3
0.1 F
C4
0.1 F
AD9632A
Gain
+10
2 k
221
49.9
100
49.9
20
R
R
O
O
C5
10 F
C6
10 F
OUT
OUT
+100
2 k
20.5
49.9
100
49.9
3