AD9857 Analog Devices, AD9857 Datasheet - Page 17

• Manufacturer Part Number: AD9857
• Description: CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
• Manufacturer: Analog Devices

The AD9857 provides true and complemented current outputs
on A
set by the RSET resistor at DAC_RSET. The value of RSET for a
particular IOUT is determined using the following equation:
For example, if a full-scale output current of 20 mA is desired,
then RSET = (39.93/0.02), or approximately 2 k . Every doubling
of the RSET value will halve the output current.
The full-scale output current range of the AD9857 is 5 mA–
20 mA. Full-scale output currents outside of this range will
degrade SFDR performance. SFDR is also slightly affected by
output matching; the two outputs should be terminated equally
for best SFDR performance.
The output load should be located as close as possible to the
AD9857 package to minimize stray capacitance and inductance.
The load may be a simple resistor to ground, an op amp current-
to-voltage converter, or a transformer-coupled circuit.
Driving an LC filter without a transformer requires that the fil-
ter be doubly terminated for best performance. Therefore, the
filter input and output should both be resistively terminated with
the appropriate values. The parallel combination of the two ter-
minations will determine the load that the AD9857 will see for
signals within the filter pass band. For example, a 50
nated input/output low-pass filter will look like a 25
the AD9857.
The output compliance voltage of the AD9857 is –0.5 V to +1.0 V.
Any signal developed at the DAC output should not exceed 1.0 V,
otherwise, signal distortion will result. Furthermore, the sig-
nal may extend below ground as much as 0.5 V without damage
or signal distortion. The use of a transformer with a grounded
center-tap for common-mode rejection results in signals at the
AD9857 DAC output pins that are symmetrical about ground.
As previously mentioned, by differentially combining the two
signals the user can provide some degree of common-mode
signal rejection. A differential combiner might consist of a trans-
former or an op amp. The object is to combine or amplify only
the difference between two signals and to reject any common,
usually undesirable, characteristic, such as 60 Hz hum or “clock
feed-through” that is equally present on both input signals. The
AD9857 true and complement outputs can be differentially
combined using a broadband 1:1 transformer with a grounded,
center-tapped primary to perform differential combining of the
two DAC outputs.
Reference Clock Multiplier
It is often difficult to provide a high-quality oscillator with an out-
put in the frequency range of 100 MHz–200 MHz. The AD9857
allows the use of a lower-frequency oscillator that can be multi-
plied to a higher frequency by the on-board Reference Clock
Multiplier, implemented with a Phase Locked Loop architec-
ture. See the Ease of Use section for a more thorough discussion
of the Reference Clock Multiplier feature.
OUT
and AOUT respectively. The full-scale output current is
RSET = 39.93/IOUT
load to
termi-
INPUT DATA PROGRAMMING
Control Interface—Serial I/O
The AD9857 serial port is a flexible, synchronous, serial communi-
cations port allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compat-
ible with most synchronous transfer formats, including both the
Motorola 6905/11 SPI and Intel 8051 SSR protocols.
The interface allows read/write access to all registers that config-
ure the AD9857. Single or multiple byte transfers are supported
as well as MSB first or LSB first transfer formats. The AD9857’s
serial interface port can be configured as a single pin I/O (SDIO)
or two unidirectional pins for in/out (SDIO/SDO).
General Operation of the Serial Interface
There are two phases to a communication cycle with the AD9857.
Phase 1 is the instruction cycle, which is the writing of an instruc-
tion byte into the AD9857, coincident with the first eight SCLK
rising edges. The instruction byte provides the AD9857 serial port
controller with information regarding the data transfer cycle,
which is Phase 2 of the communication cycle. The Phase 1 instruc-
tion byte defines whether the upcoming data transfer is read or
write, the number of bytes in the data transfer (1–4), and the
starting register address for the first byte of the data transfer.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9857. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9857
and the system controller. Phase 2 of the communication cycle
is a transfer of 1, 2, 3, or 4 data bytes as determined by the
instruction byte. Normally, using one communication cycle in a
multibyte transfer is the preferred method. However, single byte
communication cycles are useful to reduce CPU overhead when
register access requires one byte only. An example of this may
be to write the AD9857 SLEEP bit.
At the completion of any communication cycle, the AD9857
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle.
All data input to the AD9857 is registered on the rising edge of
SCLK. All data is driven out of the AD9857 on the falling edge
of SCLK.
AD9857