AD9889 Analog Devices, AD9889 Datasheet - Page 12

• Manufacturer Part Number: AD9889
• Description: High Performance HDMI/DVI Transmitter
• Manufacturer: Analog Devices

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AD9889
YCbCr 4:2:2 DDR (Double Data Rate) Formats (12 Bits, 10 Bits, or 8 Bits) with Embedded Syncs. Input ID = 4
An input with YCbCr 4:2:2 DDR data and embedded syncs (ITU 656) can be selected by setting the input ID (R0x15[3:1]) to 0b100. The
input CS (R0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with R0x16[5:4]. The two input pin
assignment styles are shown in Table 14. The input style can be set in R0x16[3:2]. The order of data input is the order in the table (for
example, 12-bit data is accepted as Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3).
Table 14.
Input Format
12-bit
10-bit
8-bit
12-bit
10-bit
8-bit
Normal 4:4:4 input format (RGB or YCbCr) Clocked at Double Data Rate (DDR), Input ID = 5
An input with YCbCr 4:2:2 DDR data and separate syncs can be selected by setting the input ID (R0x15[3:1]) to 0b011. The input CS
(R0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with R0x16[5:4]. The three input pin assignment
styles are shown in Table 15. The input style can be set in R0x16[3:2].
Table 15.
Input Format
RGB 4:4:4 (DDR)
(1
2
YCbCr 4:4:4 (DDR)
(1
2
RGB 4:4:4 (DDR)
(1
2
YCbCr 4:4:4 (DDR)
(1
2
YCbCr 4:4:4 (DDR)
(1
2
nd
nd
nd
nd
nd
st
st
st
st
st
edge)
edge)
edge)
edge)
edge)
edge,
edge,
edge,
edge,
edge,
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Cb/Y/Cr/Y[11:4]
Cb/Y/Cr/Y[9:2]
Cb/Y/Cr/Y[7:0]
Style 1
Style 2
Style 1
Style 2
Style 3
15
14
Data <23:0>
14
Data <23:0>
13
13
12
12
11
Cb/Y/Cr/Y[11:0]
11
G[3:0]
R[7:0]
Y[3:0]
Cr[7:0]
R[7:0]
G[3:0]
Cr[7:0]
Y[3:0]
Y[7:0]
Cb[3:0]
10
10
9
Cb/Y/Cr/Y[9:0]
9
8
8
B[7:0]
Cb[7:0]
B[7:0]
Cb[7:0]
Cr[7:0]
7
Cb/Y/Cr/Y[7:0]
7
6
6
5
5
4
4
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G[7:4]
Y[7:4]
G[7:4]
Y[7:4]
Cb[7:4]
3
[3:0]
[1:0]
3
2
2
1
1
0
0
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