AD9995 Analog Devices, AD9995 Datasheet - Page 12

• Manufacturer Part Number: AD9995
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: Analog Devices

AD9995
(INTERNAL)
CCDIN
DCLK
DOUT
SHD
CLI
NOTES
DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0, DCLKMODE = 0.
HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
POSITION
PERIOD
SIGNAL
PERIOD
PIXEL
H1/H3
H2/H4
PIXEL
DOUT
NOTES
DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.
OUTPUT DELAY (
DCLK
CCD
RG
t
N–13
CLIDLY
N–1
NOTES
ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
P[0]
N–12
N
P[0]
SAMPLE PIXEL N
t
RGr[0]
OD
Hr[0]
) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
N–11
N+1
t
OD
Figure 7. High SpeedTiming Default Locations
Figure 8a. Digital Output Phase Adjustment
N+2
N–10
P[12]
N+3
N–9
RGf[12]
P[12]
Figure 8b. Pipeline Delay
N+4
N–8
PIPELINE LATENCY=11 CYCLES
N+5
N–7
–12–
P[24]
SHP[24]
P[24]
N+6
Hf[24]
N–6
N+7
N–5
N+8
N–4
P[36]
P[36]
N+9
N–3
t
S1
N+10
N–2
P[48] = P[0]
N+11
N–1
P[48] = P[0]
SHD[0]
N+12
N
N+13
N+1
N+2
REV. 0