AD9995 Analog Devices, AD9995 Datasheet - Page 53

• Manufacturer Part Number: AD9995
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: Analog Devices

Address Content Value
B8
B9
BA
BB
BC
BD
BE
BF
Address Content Value
C0
C1
C2
C3
C4
C5
C6
C7
REV. 0
Data Bit Default
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
Data Bit Default
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Name
HBLKMASK_7
CLPOBPOL_7
CLPOBPOL_7
CLPOBPOL
PBLKPOL_7
PBLKPOL_7
PBLKPOL
VPATSEL_7
VPATSEL_7
VPATSEL
VMASK_7
VMASK_7
VMASK
HBLKALT_7
UNUSED
VPATREPO_7
VPATREPE_7
VPATSTART_7
HDLEN_7
PBLKTOG1_7
PBLKTOG2_7
HBLKTOG1_7
HBLKTOG2_7
HBLKTOG3_7
HBLKTOG4_7
HBLKTOG5_7
HBLKTOG6_7
CLPOBTOG1_7
CLPOBTOG2_7
Register Name
HBLKMASK_8
CLPOBPOL_8
CLPOBPOL_8
CLPOBPOL
PBLKPOL_8
PBLKPOL_8
PBLKPOL
VPATSEL_8
VPATSEL_8
VPATSEL
VMASK_8
VMASK_8
VMASK
HBLKALT_8
UNUSED
VPATREPO_8
VPATREPE_8
VPATSTART_8
HDLEN_8
PBLKTOG1_8
PBLKTOG2_8
HBLKTOG1_8
HBLKTOG2_8
HBLKTOG3_8
HBLKTOG4_8
HBLKTOG5_8
HBLKTOG6_8
CLPOBTOG1_8
CLPOBTOG2_8
Table XLIV. V-Sequence 7 (VSEQ7) Register Map
Table XLV. V-Sequence 8 (VSEQ8) Register Map
Description
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 7
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
Enable HBLK Alternation
Unused
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 7
PBLK Toggle Position 1 for V-Sequence 7
PBLK Toggle Position 2 for V-Sequence 7
HBLK Toggle Position 1 for V-Sequence 7
HBLK Toggle Position 2 for V-Sequence 7
HBLK Toggle Position 3 for V-Sequence 7
HBLK Toggle Position 4 for V-Sequence 7
HBLK Toggle Position 5 for V-Sequence 7
HBLK Toggle Position 6 for V-Sequence 7
CLPOB Toggle Position 1 for V-Sequence 7
CLPOB Toggle Position 2 for V-Sequence 7
Description
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 8
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
Enable HBLK Alternation
Unused
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 8
PBLK Toggle Position 1 for V-Sequence 8
PBLK Toggle Position 2 for V-Sequence 8
HBLK Toggle Position 1 for V-Sequence 8
HBLK Toggle Position 2 for V-Sequence 8
HBLK Toggle Position 3 for V-Sequence 8
HBLK Toggle Position 4 for V-Sequence 8
HBLK Toggle Position 5 for V-Sequence 8
HBLK Toggle Position 6 for V-Sequence 8
CLPOB Toggle Position 1 for V-Sequence 8
CLPOB Toggle Position 2 for V-Sequence 8
–53–
AD9995