AD9215-65 Analog Devices, AD9215-65 Datasheet - Page 11

• Manufacturer Part Number: AD9215-65
• Description: 10-Bit, 65/80/105 MSPS 3.3 V A/D Converter
• Manufacturer: Analog Devices

TIMING
The AD9215 provides latched data outputs with a pipeline delay
of five clock cycles. Data outputs are available one propagation
delay (t
Figure 1 for a detailed timing diagram.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9215;
these transients can detract from the converter’s dynamic
performance.
The lowest typical conversion rate of the AD9215 is 1 MSPS.
At clock rates below 1 MSPS, dynamic performance may degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9215. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9215, using either the internal
reference or an externally applied reference voltage. The input
span of the A/D tracks reference voltage changes linearly.
INTERNAL REFERENCE CONNECTION
A comparator within the AD9215 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table I. If SENSE is grounded,
the reference amplifier switch is connected to the internal resis-
tor divider (see Figure 12), setting VREF to 1 V. Connecting
the SENSE pin to the VREF pin switches the amplifier output
to the SENSE pin, configuring the internal op amp circuit as a
voltage follower and providing a 0.5 V reference output. If an
external resistor divider is connected as shown in Figure 13, the
switch will again be set to the SENSE pin. This will put the
reference amplifier in a noninverting mode with the VREF out-
put defined as follows:
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the A/D always equals twice the voltage at the reference pin for
either an internal or an external reference.
REV. PrA
10 F
OD
Figure 12. Internal Reference Configuration
VREF
) after the rising edge of the clock signal. Refer to
SENSE
0.1 F
VIN–
VREF
VIN+
=
0 5
.
×
7k
7k
(
1
+
SELECT
LOGIC
R
2
/
R
1
AD9215
)
CORE
ADC
0.5V
REFT
REFB
0.1 F
0.1 F
0.1 F
10 F
–11–
EXTERNAL REFERENCE OPERATION
The use of an external reference may be necessary to enhance
the gain accuracy of the A/D or improve thermal drift character-
istics. When multiple A/Ds track one another, a single reference
(internal or external) may be necessary to reduce gain matching
errors to an acceptable level. A high precision external reference
may also be selected to provide lower gain and offset tempera-
ture drift. Figure 14 shows the typical drift characteristics of the
internal reference in both 1 V and 0.5 V modes.
When the SENSE pin is tied to AVDD, the internal reference
will be disabled, allowing the use of an external reference. An
internal reference buffer will load the external reference with an
equivalent 7 kΩ load. The internal buffer will still generate the
positive and negative full-scale references, REFT and REFB, for
the A/D core. The input span will always be twice the value of
the reference voltage; therefore, the external reference must be
limited to a maximum of 1 V.
If the internal reference of the AD9215 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 15
depicts how the internal reference voltage is affected by loading.
10 F
Figure 13. Programmable Reference Configuration
1.2
1.0
0.8
0.6
0.4
0.2
0.0
–40
SENSE
0.1 F
–30 –20 –10
R
R
VREF
VIN+
2
1
VIN–
Figure 14. Typical VREF Drift
0
SELECT
TEMPERATURE – C
LOGIC
10
20
AD9215
30
CORE
40
ADC
0.5V
50
V
V
60
REFT
REFB
AD9215
REF
REF
0.1 F
0.1 F
0.1 F
70
= 1.0V
= 0.5V
80
80
10 F