LM5035A-1 National Semiconductor, LM5035A-1 Datasheet - Page 21

• Manufacturer Part Number: LM5035A-1
• Description: PWM Controller
• Manufacturer: National Semiconductor

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T1 and T2 can be set to minimum by not connecting a resistor
to DLY, connecting a resistor greater than 300kΩ from DLY
to ground, or connecting DLY to the REF pin. This may cause
lower than optimal system efficiency if the delays through the
SR signal transformer network, the secondary gate drivers
and the SR MOSFETs are greater than the delay to turn on
the HO or LO MOSFETs. Should an SR MOSFET remain on
while the opposing primary MOSFET is supplying power
through the power transformer, the secondary winding will
experience a momentary short circuit, causing a significant
power loss to occur.
When choosing the R
lays and component tolerances should be considered to as-
sure that there is never a time where both SR MOSFETs are
enabled AND one of the primary side MOSFETs is enabled.
The time period T1 should be set so that the SR MOSFET has
turned off before the primary MOSFET is enabled. Converse-
ly, T1 and T2 should be kept as low as tolerances allow to
optimize efficiency. The SR body diode conducts during the
time between the SR MOSFET turns off and the power trans-
former begins supplying energy. Power losses increase when
this happens since the body diode voltage drop is many times
higher than the MOSFET channel voltage drop. The interval
of body diode conduction can be observed with an oscillo-
scope as a negative 0.7V to 1.5V pulse at the SR MOSFET
drain.
UVLO AND OVP VOLTAGE DIVIDER SELECTION FOR R1,
R2, AND R3
Two dedicated comparators connected to the UVLO and OVP
pins are used to detect under-voltage and over-voltage con-
ditions. The threshold value of these comparators, V
V
grammed independently with two voltage dividers from VIN to
OVP
, is 1.25V (typical). The two functions can be pro-
T2 = .0007 x R
DLY
value, worst case propagation de-
DLY
+ 10.01 ns
FIGURE 10. Basic UVLO Configuration
UVLO
and
21
AGND as shown in
resistor divider as shown in
and OVP pins provide greater flexibility for the user to select
the operational voltage range of the system. Hysteresis is ac-
complished by 23 µA current sources (I
are switched on or off into the sense pin resistor dividers as
the comparators change state.
When the UVLO pin voltage is below 0.4V, the controller is in
a low current shutdown mode. For a UVLO pin voltage greater
than 0.4V but less than 1.25V the controller is in standby
mode. Once the UVLO pin voltage is greater than 1.25V, the
controller is fully enabled. Two external resistors can be used
to program the minimum operational voltage for the power
converter as shown in
falls below the 1.25V threshold, an internal 23 µA current sink
is enabled to lower the voltage at the UVLO pin, thus providing
threshold hysteresis. Resistance values for R1 and R2 can
be determined from the following equations.
where V
desired UVLO hysteresis at V
For example, if the LM5035A is to be enabled when V
reaches 34V, and disabled when VPWR is decreased to 32V,
R1 should be 87 kΩ, and R2 should be 3.54kΩ. The voltage
at the UVLO pin should not exceed 7V at any time. Be sure
to check both the power and voltage rating (0603 resistors
can be rated as low as 50V) for the selected R1 resistor.
PWR
is the desired turn-on voltage and V
Figure 10
Figure
10. When the UVLO pin voltage
Figure
PWR
and
30034129
.
Figure
12. Independent UVLO
UVLO
11, or with a three-
and I
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OVP
HYS
), which
is the
PWR