MAX106CHC Maxim, MAX106CHC Datasheet - Page 13

• Manufacturer Part Number: MAX106CHC
• Description: 5V / 600Msps / 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
• Manufacturer: Maxim

The MAX106’s flash or parallel architecture provides
the fastest multibit conversion of all common integrated
ADC designs. The key to this high-speed flash archi-
tecture is the use of an innovative, high-performance
comparator design. The flash converter and down-
stream logic translate the comparator outputs into a
parallel 8-bit output code and pass this binary code on
to the optional 8:16 demultiplexer, where primary and
auxiliary ports output PECL-compatible data at up to
300Msps per port (depending on how the demultiplex-
er section is set on the MAX106). The ideal transfer
function appears in Figure 2.
As with all ADCs, if the input waveform is changing
rapidly during conversion, ENOB and signal-to-noise
ratio (SNR) specifications will degrade. The MAX106’s
on-chip, wide-bandwidth (2.2GHz) T/H amplifier reduces
this effect and increases the ENOB performance signifi-
cantly, allowing precise capture of fast analog data at
high conversion rates.
The T/H amplifier buffers the input signal and allows a
full-scale signal input range of ±250mV. The T/H ampli-
fier’s differential 50Ω input termination simplifies inter-
facing to the MAX106 with controlled impedance lines.
Figure 3 shows a simplified diagram of the T/H amplifier
stage internal to the MAX106.
Aperture width, delay, and jitter (or uncertainty) are
parameters that affect the dynamic performance of
high-speed converters. Aperture jitter, in particular,
directly influences SNR and limits the maximum slew
rate (dV/dt) that can be digitized without a significant
contribution of errors. The MAX106’s innovative T/H
amplifier design typically limits aperture jitter to less
than 0.5ps.
Aperture width (t
(Figure 4) to disconnect the hold capacitor from the
input circuit (for instance to turn off the sampling bridge
and put the T/H unit in hold mode).
Aperture jitter (t
(Figure 4) in the time between the samples.
Aperture delay (t
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 4).
AJ
AW
AD
On-Chip Track/Hold Amplifier
______________________________________________________________________________________
) is the sample-to-sample variation
) is the time the T/H circuit requires
2.2GHz Bandwidth Track/Hold Amplifier
) is the time defined between the
±5V, 600Msps, 8-Bit ADC with On-Chip
Principle of Operation
Aperture Width
Aperture Delay
Aperture Jitter
Figure 3. Internal Structure of the 2.2GHz T/H Amplifier
Figure 2. Transfer Function
Figure 4. T/H Aperture Timing
CLKCOM
ALL INPUTS ARE ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
CLK+
CLK-
VIN+
VIN-
OVERRANGE + 255
DATA (T/H)
50
50
SAMPLED
ANALOG
INPUT
GNDI
CLK
CLK
T/H
t
255
254
129
128
127
126
AD
3
2
1
0
TRACK
50
50
AMPLIFIER
SPLITTER
CLOCK
INPUT
APERTURE DELAY (t
APERTURE WIDTH (t
APERTURE JITTER (t
ANALOG INPUT
SAMPLING
t
t
BRIDGE
AW
HOLD
AJ
0
GNDI
AD
AJ
AW
)
)
)
AMPLIFIER
C
BUFFER
TO
COMPARATORS
HOLD
TRACK
TO
COMPARATORS
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