MAX1167 Maxim, MAX1167 Datasheet - Page 20

• Manufacturer Part Number: MAX1167
• Description: Multichannel / 16-Bit / 200ksps Analog-to-Digital Converters
• Manufacturer: Maxim

Force DSPR high and DSEL low for the SPI/QSPI/
MICROWIRE interface mode. The falling edge of CS
wakes the analog circuitry and allows SCLK to clock in
data (Figure 13). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the
rising edge of SCLK. The command/configuration/con-
trol register begins reading DIN on the first SCLK rising
edge and ends on the rising edge of the 8th SCLK
cycle. The MAX1168 selects the proper channel for
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1168 Only)
Figure 16. Detailed DSP-Interface Timing (MAX1168 Only)
20
INTERNAL
Internal Clock 16-Bit-Wide Data-Transfer and Scan
STATE
DOUT
SCLK
______________________________________________________________________________________
ADC
CLK
EOC
DIN
CS
1
X = DON
DATA
• • •
,
T CARE
DSPR
DOUT
SCLK
DIN
8
CS
9
X X X X X X X X
• • •
t
CSW
16
Mode (MAX1168 Only)
t
DF
t
CSS
2
t
DV
t
CP
t
ACQ
t
FSH
• • •
t
CL
t
FSS
13
t
CH
t
• • •
DS
t
CONV
32
t
DH
...
...
...
...
...
conversion on the rising edge of the 3rd SCLK cycle.
The internal oscillator activates 125ns after the rising
edge of the 16th SCLK cycle. Turn off the external clock
while the internal clock is on. Turning off SCLK ensures
lowest noise performance during acquisition.
Acquisition begins on the 2nd rising edge of the inter-
nal clock and ends on the falling edge of the 18th inter-
nal clock cycle. Each bit of the conversion result shifts
into memory as it becomes available. The conversion
result is available (MSB first) at DOUT on the falling
edge of EOC. The internal oscillator and analog circuitry
34
• • •
t
ACQ
t
DO
45
t
CONV
• • •
64
MSB
17
t
CSH
t
TR
POWER-DOWN
• • •
• • •
LSB
48
X