MAX1246 Maxim, MAX1246 Datasheet - Page 16

• Manufacturer Part Number: MAX1246
• Description: +2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16
• Manufacturer: Maxim

determines clock mode and power-down states. For
example, if the DIN word contains PD1 = 1, then the
chip remains powered up. If PD0 = PD1 = 0, a
power-down resumes after one conversion.
Pulling SHDN low places the converter in hardware
power-down (Table 6). Unlike software power-down
mode, the conversion is not completed; it stops coin-
cidentally with SHDN being brought low. SHDN also
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
Figure 11a. Timing Diagram Power-Down Modes, External Clock
Figure 11b. Timing Diagram Power-Down Modes, Internal Clock
16
CLOCK
MODE
MODE
DOUT
SHDN
CLOCK
MODE
SSTRB
MODE
DOUT
DIN
______________________________________________________________________________________
DIN
S X X X X X 1 1
S X X X X X 1 0
SETS EXTERNAL
CLOCK MODE
SETS INTERNAL
CLOCK MODE
CONVERSION
12 DATA BITS
POWERED UP
Hardware Power-Down
POWERED UP
EXTERNAL
DATA VALID
S
X
X
X
X
X
0 0
INTERNAL
SETS SOFTWARE
POWER-DOWN
S
X
X
12 DATA BITS
X
controls the clock frequency in internal clock mode.
Letting SHDN float sets the internal clock frequency to
1.8MHz. When returning to normal operation with SHDN
floating, there is a t
where C
Pulling SHDN high sets internal clock frequency to
225kHz. This feature eases the settling-time requirement
for the reference voltage. With an external reference, the
MAX1246/MAX1247 can be considered fully powered up
within 2µs of actively pulling SHDN high.
X
X
0 0
SETS
POWER-DOWN
POWER-DOWN
L
CONVERSION
SOFTWARE
is the capacitive loading on the SHDN pin.
SETS EXTERNAL
CLOCK MODE
S
X X X X X
POWERED UP
RC
delay of approximately 2MΩ x C
1 1
DATA VALID
POWER-DOWN
VALID
DATA
HARDWARE
EXTERNAL
POWER-
INVALID
DOWN
DATA
S
POWERED UP
POWERED UP
L
,