MAX1295 Maxim, MAX1295 Datasheet - Page 13

• Manufacturer Part Number: MAX1295
• Description: 265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel Interface
• Manufacturer: Maxim

Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
To select the external clock mode, bits D6 and D7 of
the control byte must be set to zero. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1295/MAX1297 with
CLK
CLK
WR
WR
CLK
CLK
WR
WR
with +2.5V Reference and Parallel Interface
ACQMOD = "1"
ACQMOD = "1"
t
CWH
______________________________________________________________________________________
ACQMOD = "0"
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
t
CWS
ACQMOD = "0"
ACQUISITION STARTS
ACQUISITION STARTS
ACQUISITION STARTS
t
t
DH
DH
External Clock Mode
ACQUISITION STARTS
t
CH
t
CP
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
t
CL
WR GOES HIGH WHEN CLK IS LOW.
WR GOES HIGH WHEN CLK IS HIGH.
ACQUISITION ENDS
ACQUISITION ENDS
clock frequencies lower than 100kHz is not recommend-
ed because the resulting voltage droop across the hold
capacitor in the T/H stage will degrade performance.
The input and output data are multiplexed on a three-
state parallel interface (I/O) that can easily be inter-
faced with standard µPs. The signals CS, WR, and RD
control the write and read operations. CS represents
ACQUISITION ENDS
CONVERSION STARTS
t
CWH
CONVERSION STARTS
ACQUISITION ENDS
ACQMOD = "0"
ACQMOD = "0"
t
CWS
Digital Interface
CONVERSION STARTS
CONVERSION STARTS
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