MAX144 Maxim, MAX144 Datasheet - Page 4

• Manufacturer Part Number: MAX144
• Description: +2.7V / Low-Power / 2-Channel / 108ksps / Serial 12-Bit ADCs in 8-Pin MAX
• Manufacturer: Maxim

TIMING CHARACTERISTICS (Figure 7)
(V
CH- = GND for MAX145, T
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
Note 1: Tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
Note 3: Offset nulled.
Note 4: “On” channel is grounded; sine wave applied to “off” channel (MAX144 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to V
Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as V
Note 10: SCLK must remain stable during this time.
4
Wake-Up Time (Note 10)
CS/SHDN Fall to Output Enable
CS/SHDN Rise to Output Disable
SCLK Fall to Output Data Valid
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK to CS/SHDN Setup
CS/SHDN Pulse Width
DD
_______________________________________________________________________________________
= +2.7V to +5.25V, V
calibrated.
PARAMETER
DD
= +2.7V.
FS(2.7V)
A
= T
REF
MIN
- V
= 2.5V, 0.1µF capacitor at REF, f
SYMBOL
to T
FS(5.25V)
t
t
f
SCLKS
WAKE
SCLK
t
t
t
t
t
t
DO
CH
DV
TR
CL
CS
MAX
, unless otherwise noted. Typical values are at T
.
C
C
C
External clock
Internal clock, SCLK for data transfer only
External clock
Internal clock, SCLK for data transfer only
(Note 8)
External clock
Internal clock, SCLK for data transfer only
(Note 8)
L
L
L
= 100pF, Figure 1
= 100pF
= 100pF, Figure 1
CONDITIONS
SCLK
DD
= 2.17MHz, 16 clocks/conversion cycle (108ksps),
(MAX145 only).
A
MIN
215
215
2.5
0.1
= +25°C.)
20
50
50
60
60
0
TYP
MAX
2.17
120
120
120
5
UNITS
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns