MAX1497 Maxim, MAX1497 Datasheet - Page 10

• Manufacturer Part Number: MAX1497
• Description: 3.5- and 4.5-Digit / Single-Chip ADCs with LED Drivers and C Interface
• Manufacturer: Maxim

3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and µC Interface
10
MAX1497
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10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
PIN
MAX1499
31
32
10
11
12
13
14
15
16
17
18
20
21
22
23
24
—
1
2
3
4
5
8
9
NAME
VNEG
DOUT
SEGC
SEGD
GLED
SEGA
SEGB
SEGE
REF+
SCLK
AIN+
DIG0
DIG1
DIG2
DIG3
REF-
GND
AIN-
EOC
V
CLK
I
DIN
CS
SET
DD
-2.5V Charge-Pump Voltage-Output. Connect a 0.1µF capacitor to GND.
Negative Reference Voltage Input. For internal reference operation, connect REF- to
GND. For external reference operation, bypass REF- to GND with a 0.1µF capacitor and
set V
Positive Reference Voltage Input. For internal reference operation, connect a 4.7µF
capacitor from REF+ to GND. For external reference operation, bypass REF+ to GND
with a 0.1µF capacitor and set V
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND
with a 0.1µF or greater capacitor.
Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to
GND with a 0.1µF or greater capacitor.
Segment Current Controller. Connect to ground through a resistor to set the segment
current. See Table 6 for segment current selection.
Ground
Analog and Digital Circuit Supply Voltage. Connect V
supply. Bypass V
External Clock Input. When the EXTCLK register bit is set to one, CLK is the master clock
input (frequency = 4.9152MHz) for the modulator and the filter. When the EXTCLK
register bit is reset to zero, the internal clock is used. Connect CLK to GND or DV
(MAX1499) or V
Active-Low End-of-Conversion Logic Output. A logic low at EOC indicates that a new
ADC result is available in the ADC result register.
Active-Low Chip Select Input. Forcing CS low activates the serial interface.
Serial Data Input. Data present at DIN is shifted into the internal registers in response to
a rising edge at SCLK when CS is low.
Serial Clock Input. Apply an external clock to SCLK to facilitate communication through
the serial bus. SCLK may idle high or low.
Serial Data Output. DOUT presets serial data in response to register queries. Data shifts
out on the falling edge of SCLK. DOUT goes high impedance when CS is high.
Digit 0 Driver
Digit 1 Driver
Ground for LED-Display Segment Driver
Digit 2 Driver
Digit 3 Driver
Segment A Driver
Segment B Driver
Segment C Driver
Segment D Driver
Segment E Driver
REF-
from -2.2V to +2.2V, provided V
DD
DD
(MAX1497) when the internal oscillator is used.
to GND with a 0.1µF and a 4.7µF capacitor.
REF+
from -2.2V to +2.2V, provided V
FUNCTION
REF+
> V
REF-
DD
.
to a +2.7V to +5.25V power
Pin Description
REF+
> V
REF-
DD
.