MAX1497 Maxim, MAX1497 Datasheet - Page 19

• Manufacturer Part Number: MAX1497
• Description: 3.5- and 4.5-Digit / Single-Chip ADCs with LED Drivers and C Interface
• Manufacturer: Maxim

START: Start bit. The first 1 clocked into the MAX1497/
MAX1499 is the first bit of the command byte.
(R/W): Read/Write. Set this bit to 1 to read from the
specified register. Set this bit to zero to write to the
selected register. Note that certain registers are read
Default values: 00h
This register contains the status of the conversion
results.
SIGN: Latched negative-polarity indicator. Latches
high when the result is negative. Clears by reading the
status register, unless the condition remains true.
OVER: Overrange bit. Latches high if an overrange
condition occurs (the ADC result is larger than the
value in the overrange register). Clears by reading the
status register, unless the condition remains true.
UNDER: Underrange bit. Latches high if an under-
range condition occurs (the ADC result is less than the
Command Byte (Write Only)
Status Register (Read Only)
Default values: 0000h
This register is the primary control register for the
MAX1497/MAX1499. It is a 16-bit read/write register. It
is used to indicate the desired clock and reference
source. It sets the LED display controls, range modes,
power-down modes, offset calibration, and the reset
register function (CLR).
Control Register (Read/Write)
MSB
MSB
MSB
START(1)
SPI/ADC
SIGN
HOLD
Bit 15
Bit 7
Bit 7
3.5- and 4.5-Digit, Single-Chip ADCs with LED
Control and Status Registers
EXTCLK
______________________________________________________________________________________
OVER
Bit 14
PEAK
Bit 6
Bit 6
R/W
RANGE
INTREF
UNDER
Bit 13
Bit 5
Bit 5
RS4
LOW_BATT
DPON
Bit 12
Bit 4
CLR
Bit 4
RS3
Drivers and µC Interface
only. Write commands to a read-only register are
ignored.
(RS4–RS0): Register address bits. RS4 to RS0 specify
which register is accessed.
X: Don’t care.
value in the underrange register). Clears by reading the
status register, unless the condition remains true.
LOW_BATT: Low-battery bit. Latches high if the volt-
age at the LOWBATT is lower than 2.048V (typ). Clears
by reading the status register, unless the condition
remains true. For the MAX1497, LOWBATT is not used
and the LOWBATT bit always returns to zero.
DRDY: Data ready bit. Latches high to indicate a com-
pleted conversion result with valid data. Read the ADC
result register to clear this bit.
SEG_SEL
ENABLE: (default = 1) LED driver enable bit. When set to
1, the MAX1497/MAX1499 enables the LED display dri-
vers. A 0 in this location disables the LED display drivers.
OFFSET_CAL2: (default = 0) Enhanced offset-calibra-
tion start bit (MAX1499, RANGE = 1). To achieve the
lowest possible offset in the ±200mV input range, per-
form an enhanced offset calibration by setting this bit to
DPSET2
Bit 11
Bit 3
DRDY
Bit 3
RS2
OFFSET_CAL1
DPSET1
Bit 10
Bit 2
Bit 2
RS1
0
OFFSET_
PD_DIG
Bit 1
RS0
CAL2
0
Bit 9
Bit 1
PD_ANA
ENABLE
Bit 0
0
Bit 8
Bit 0
X
LSB
LSB
LSB
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