MAX15023 Maxim Integrated Products, MAX15023 Datasheet - Page 18

• Manufacturer Part Number: MAX15023
• Description: Dual-Output Synchronous Buck Controller
• Manufacturer: Maxim Integrated Products

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Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
The minimum current-limit threshold must be high
enough to support the maximum expected load current
with the worst-case low-side MOSFET on-resistance
value since the low-side MOSFET’s on-resistance is
used as the current-sense element. The inductor’s
cycle-by-cycle, low-side, source peak current occurs at
I
rent is maximum when the inductor value is at the lower
limit of its specified tolerance. The minimum value of
the current-limit threshold voltage (V
greater than the voltage on the low-side MOSFET dur-
ing the ripple-current valley:
where R
MOSFET in ohms. Use the maximum value for R
from the low-side MOSFET’s data sheet.
To adjust the current-limit threshold, connect a resistor
(R
the current-limit threshold (V
where R
An R
to a current-limit threshold of 30mV to 300mV. When
adjusting the current limit, use 1% tolerance resistors to
minimize errors in the current-limit threshold setting.
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The two converters of the MAX15023 run 180° out-of-
phase, thereby, effectively doubling the switching fre-
quency at the input and lowering the input RMS current.
The input ripple waveform would be unsymmetrical due
to the difference in load current and duty cycle between
converter 1 and converter 2. In fact, the worst-case input
RMS current occurs when only one controller is operat-
ing. The converter delivering the highest output power
(V
The input capacitor RMS current requirement (I
defined by the following equation:
18
LOAD(MAX)
OUT
LIM
______________________________________________________________________________________
LIM_
) from LIM_ to SGND. The relationship between
V
x I
ITH
Setting the Cycle-by-Cycle, Low-Side,
LIM_
I
OUT
RMS
DS(ON)
resistance range of 6kΩ to 60kΩ corresponds
>
minus half the ripple current. The ripple cur-
R
) must be used in the formulas below:
is in kΩ and V
=
DS ON MAX
I
LOAD MAX
(
is the on-resistance of the low-side
R
LIM
,
(
Source Peak Current Limit
_
)
=
×
)
ITH_
10
I
LOAD MAX
ITH
V
50μ
×
OUT IN
) and R
is in mV.
V
ITH
(
A
(
V
V
Input Capacitor
_
IN
)
LIM_
−
×
V
ITH
⎛
⎜
⎝
OUT
1
−
) should be
is:
LIR
)
2
⎞
⎟
⎠
RMS
DS(ON)
) is
I
equals twice the output voltage (V
I
Choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
long-term reliability.
The input voltage ripple is composed of ΔV
by the capacitor discharge) and ΔV
ESR of the capacitor). Use low-ESR ceramic capacitors
with high ripple current capability at the input. Assume
the contribution from the ESR and capacitor discharge
are equal to 50%. Calculate the input capacitance and
ESR required for a specified input voltage ripple using
the following equations:
where:
and:
where:
All equations listed above are valid under the assump-
tion that the input ports of both converters can be
merged in the physical layout, so that only one input
capacitor truly serves both converters. If this is not the
case, additional low-ESR, low-ESL ceramic capacitors
should be locally placed on each converter’s input port,
connected between the drain of the high-side MOSFET
and the source of the low-side MOSFET.
The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple volt-
age, and transient response. The output ripple has two
components: variations in the charge stored in the out-
put capacitor, and the voltage drop across the capaci-
tor’s ESR caused by the current flowing into and out of
the capacitor:
RMS
RMS(MAX)
has a maximum value when the input voltage
= I
LOAD(MAX)
ΔI
Δ
V
L
ESR
C
RIPPLE
=
IN
(
IN
V
=
IN
D
I
/2.
OUT
=
V
=
−
≅
Δ
IN
I
OUT
V
V
Δ
V
OUT
Q
×
OUT
V
Δ
V
×
IN
ESR
V
f
×
SW
D
ESR
+
(
f
)
1
SW
×
Δ
Output Capacitor
−
+
×
2
I
V
D
L
L
Δ
ESR
OUT
)
V
IN
Q
(caused by the
= 2V
Q
OUT
(caused
), so