ATA8741 ATMEL Corporation, ATA8741 Datasheet - Page 184

• Manufacturer Part Number: ATA8741
• Manufacturer: ATMEL Corporation

28.6
184
Serial Downloading
ATA8741
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
Figure 28-1. Serial Programming and Verify
Note:
Table 28-9.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
Symbol
MOSI
MISO
SCK
CLKI pin.
Pin Mapping Serial Programming
MOSI
MISO
SCK
ck
ck
Pins
PA6
PA5
PA4
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
RESET
GND
(1)
VCC
I/O
O
I
I
+1.8 - 5.5V
Table 28-9 on page
ck
ck
>= 12 MHz
>= 12 MHz
Description
Serial Data in
Serial Data out
Serial Clock
9140B–INDCO–07/09
184, the pin