MAX1717 Maxim, MAX1717 Datasheet - Page 22

• Manufacturer Part Number: MAX1717
• Description: Dynamically Adjustable / Synchronous Step-Down Controller for Notebook CPUs
• Manufacturer: Maxim

Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Figure 9. Using the Internal Mux with Both VID Codes Resistor Programmed
other ICs that operate in two or more modes with differ-
ent core voltage levels.
Intel’s mobile Pentium III CPU with SpeedStep technol-
ogy operates at two distinct clock frequencies and
requires two distinct core voltages. When transitioning
from one clock frequency to the other, the CPU first
goes into a low-power state, then the output voltage
and clock frequency are changed. The change must
be accomplished in 100µs or the system may halt.
At the beginning of an output voltage transition, the
MAX1717 brings the VGATE output low, indicating that
a transition is beginning. VGATE remains low during the
transition and goes high when the slew-rate controller
has set the internal DAC to the final value and one
additional slew-rate clock period has passed. The slew-
rate clock frequency (set by resistor R
fast enough to ensure that VGATE goes high within the
allowed 100µs. Alternatively, the slew-rate clock can be
set faster than necessary and VGATE’s rising edge can
be detected so that normal system operation can
resume even earlier.
The output voltage transition is performed in 25mV
steps, preceded by a 4µs delay and followed by one
22
______________________________________________________________________________________
1k
1k
2.7V TO 5.5V
1k
100k
TIME
1k
) must be set
additional clock period after which VGATE goes high if
the output voltage is in regulation. The total time for a
transition depends on R
and the accuracy of the MAX1717’s slew-rate clock,
and is not dependent on the total output capacitance.
The greater the output capacitance, the higher the
surge current required for the transition. The MAX1717
will automatically control the current to the minimum
level required to complete the transition in the calculat-
ed time, as long as the surge current is less than the
current limit set by ILIM. The transition time is given by:
where ƒ
original output voltage, and V
age. See Time Frequency Accuracy in Electrical Char-
acteristics for ƒ
The practical range of R
sponding to 2.6µs to 26µs per 25mV step. Although the
DAC takes discrete 25mV steps, the output filter makes
NOTE: USE PULL-UP FOR A-MODE 1, PULL-DOWN FOR A-MODE 0.
USE ≥ 100kΩ FOR B-MODE 1, ≤ 1kΩ FOR B-MODE 0.
SLEW
≤ µ +
4
s
= 150kHz · 120kΩ / R
SLEW
D4
D3
D2
D1
D0




ƒ
SLEW
1
accuracy.
MAX1717



TIME
1
TIME
A/B
+
V
NEW
OLD
, the voltage difference,
is 47kΩ to 470kΩ, corre-
A/B = LOW = 1.60V
A/B = HIGH = 1.35V
25
is the new output volt-
−
mV
V
NEW
TIME



, V




OLD
is the