CDB61310 Cirrus Logic, Inc., CDB61310 Datasheet - Page 4

• Manufacturer Part Number: CDB61310
• Description: T1/e1 Line Interface Units
• Manufacturer: Cirrus Logic, Inc.

4. RECEIVE CIRCUIT
The receive signal is input at either the Receive test
points, binding posts (J4, J10) or the Receive ban-
tam jack. The receive signal is transformer coupled
to the CS61310 through the transformer T1.
The receive line is terminated by resistors R1-R2 to
provide impedance matching and receiver return
loss. They are socketed so the values may be
changed according to the application. The evalua-
tion board is supplied from the factory with 50
resistors for terminating a
line. Capacitor C3 provides an AC ground refer-
ence for the differential input.
The recovered clock and data signals are available
on BNC outputs labeled RCLK, RPOS, and RNEG.
In Hardware and Host mode (with coder mode dis-
abled), data is available on the RPOS and RNEG
BNC. With coder mode enabled, data is available
on the RDATA BNC output in unipolar format and
bipolar violations are reported on the RNEG BNC
connector.
5. REFERENCE CLOCK
The CDB61310 requires a T1 reference clock for
operation. This clock can be supplied by either a
quartz crystal or an external reference. The evalua-
tion board is supplied from the factory with a
quartz crystal for T1 operations. In the case that
both the external reference and the quartz crystal
are applied, the external reference takes prece-
dence.
5.1
A quartz crystal may be inserted at socket Y1. The
quartz crystals operate at 4X the frequency of oper-
ation, or 6.176 MHz. HDR9 allows the XTAL_IN
pin to be pulled high or low to disable or enable the
jitter attenuator.
5.2
An external reference of 1.544 MHz may be provid-
ed at the REFCLK BNC input. Header HDR7 must
4
Quartz Crystal
External Reference
twisted-pair T1
be jumpered in the "MCLK" position to provide con-
nectivity to the MCLK pin of the CS61310.
5.3
The four-LED pack D1 indicates signal states on
LATN1, LATN2, LOS and NLOOP. The LOS
LED indicator illuminates when the line interface
receiver has detected a loss of signal. The NLOOP
LED indicates if Network Loopback is in opera-
tion. The LATN1/LATN2 LED’s indicate the at-
tenuation level of the received signal below the
nominal signal level. See Table 1 for details.
6. BUFFERING
Buffer U2 provides additional drive capability for
the SW1 and Host mode connections. The buffer
outputs are filtered with an (optional) RC network
(not initially populated) to reduce the transients
caused by buffer switching.
7. TRANSFORMER SELECTION
The evaluation board is supplied from the factory
with PE-64936 (1:1) and PE-65351 (1:2) trans-
formers by Pulse Engineering. The socket T1 on
the board is for the receive transformer and T2 is
for transmit. Please see Table 2 for details on trans-
formers selection.
T1 (100
LATN1
OFF
OFF
Mode
Table 2. Transformer and Resistor Default Settings
ON
ON
LED Indicators
)
Transformer
LATN2
OFF
OFF
ON
ON
Table 1. LATN Settings
1:2
TX
Attenuation Level (dB)
Transformer R1-R2 R3-R4
RX
1:1
22.5
7.5
15
CDB61310
0
50
DS440DB2
9.1