HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 5

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Figures
Figure 1: HFC-S+ block diagram.................................................................................................................. 7
Figure 2: Pin Connection .............................................................................................................................. 9
Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel) ............................................. 28
Figure 4: FIFO Data Organisation .............................................................................................................. 30
Figure 5: Function of the CONNECT register bits..................................................................................... 42
Figure 6: GCI/IOM2 bus clock and data alignment.................................................................................... 53
Figure 7: External receiver circuitry........................................................................................................... 56
Figure 8: External transmitter circuitry ...................................................................................................... 57
Figure 9: Oscillator Circuitry...................................................................................................................... 60
Figure 10: Frame structure at reference point S and T ............................................................................... 63
Figure 11: Single channel GCI format........................................................................................................ 64
Figure 12: Clock synchronisation in NT-mode .......................................................................................... 65
Figure 13: Clock synchronisation in TE-mode........................................................................................... 66
Figure 14: HFC-S+ package dimensions .................................................................................................... 67
Tables
Table 1: Mode selection................................................................................................................................ 8
Table 2: Selected I/O address after reset .................................................................................................... 16
Table 3: DMA access in processor mode ................................................................................................... 20
Table 4: SRAM and FIFO size ................................................................................................................... 33
Table 5: S/T module part numbers and manufacturer ................................................................................ 59
Table 6: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 61
Table 7: Activation/deactivation layer 1 for finite state matrix for TE...................................................... 62
Timing Diagrams
Timing diagram 1: ISA-PC bus or microprocessor access ......................................................................... 51
Timing diagram 2: SRAM access ............................................................................................................... 52
Timing diagram 3: GCI/IOM2 timing......................................................................................................... 54
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