HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 52

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
6.2
Timing diagram 2: SRAM access
%" _V '
SYMBOL
t
SYMBOL
f
t
t
t
t
t
t
CYCLE
CLK
LOW
HIGH
SRA
SRAH
SRD
CLK
f
*
For write accesses to the HFC-S+ the data lines must be stable and valid before /IOW or /DS get
low. With Intel compatible processors it may be neccessary to delay the /IOW or /DS signals.
CLK
**)
**)
important!
/ f
SRAM access
CLK
Read/Write cycle
OSC_IN frequency
Relative OSC_IN frequency deviation
OSC_IN Cycle Time
OSC_IN Low Level Width
OSC_IN High Level Width
Address Stable after OSC_IN
Address Stable Hold Time after OSC_IN
Data Out Stable after OSC_IN
CHARACTERISTICS
CHARACTERISTICS
Ç
12.288MHz
t
t
1/ f
MIN.
CLK
CLK
10ns
2ns
1ns
0
CLK
/ 3
/ 3
6 x t
MIN.
CLK
24.576MHz
:Q^eQbi " !
Cologne
Chip
MAX.
15ns
30ns
10
–
MAX.
-4
–
*)