WM8711 Wolfson Microelectronics Ltd., WM8711 Datasheet - Page 26

• Manufacturer Part Number: WM8711
• Description: Internet Audio DAC With Integrated Headphone Driver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8711
WOLFSON MICROELECTRONICS LTD
Figure 20 2-Wire Serial Interface
Notes:
1.
2.
Table 18 2-Wire MPU Interface Address Selection
To control the WM8711 on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB
first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of
two available addresses for this device (see Table 18). If the correct address is received and the R/W
bit is ‘0’, indicating a write, then the WM8711 will respond by pulling SDIN low on the next clock pulse
(ACK). The WM8711 is a write only device and will only respond to the R/W bit indicating a write. If
the address is not recognised the device will return to the idle condition and wait for a new start
condition and valid address.
Once the WM8711 has acknowledged a correct address, the controller will send eight data bits (bits
B[15]-B[8]). WM8711 will then acknowledge the sent data by pulling SDIN low for one clock pulse.
The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8711 will then
acknowledge again by pulling SDIN low.
A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a
start or stop condition is detected out of sequence at any point in the data transfer then the device
will jump to the idle condition.
After receiving a complete address and data sequence the WM8711 returns to the idle state and
waits for another start condition. Each write to a register requires the complete sequence of start
condition, device address and R/W bit followed by the 16 register address and data bits.
SDIN
SCLK
B[15:9] are Control Address Bits
B[8:0] are Control Data Bits
(DEFAULT = LOW)
START
CSB STATE
0
1
R ADDR
R/W
ACK
ADDRESS
0011010
0011011
DATA B15-8
ACK
DATA B7-0
PP Rev 1.2 November 2000
ACK
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STOP
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