WM8959 Wolfson Microelectronics Ltd., WM8959 Datasheet - Page 106

• Manufacturer Part Number: WM8959
• Description: Mobile Multimedia DAC with Dual-mode Class AB/D Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8959
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DAC SAMPLE RATES
The DAC sample rate is selectable, relative to SYSCLK, by setting the register field DAC_CLKDIV.
This field must be set according to the SYSCLK frequency, and according to the selected clocking
mode.
Two clocking modes are provided - Normal Mode (AIF_LRCLKRATE = 0) allows selection of the
commonly used sample rates from typical audio system clocking frequencies (eg. 12.288MHz); USB
Mode (AIF_LRCLKRATE = 1) allows many of these sample rates to be generated from a 12MHz
USB clock. Depending on the available clock sources, the USB mode may be used to save power by
supporting 44.1kHz operation without requiring the PLL.
The AIF_LRCLKRATE field must be set as described in Table 57 to ensure correct operation of
internal functions according to the SYSCLK / Fs ratio. Table 58 describes the available sample rates
using four different common MCLK frequencies.
In Normal mode, the programmable division set by DAC_CLKDIV must ensure that a 256 * DAC Fs
clock is generated for the DAC DSP.
In USB mode, the programmable division set by DAC_CLKDIV must ensure that a 272 * DAC Fs
clock is generated for the DAC DSP.
Note that in USB mode, the DAC sample rate does not match exactly with the commonly used
sample rates (e.g. 44.118 kHz instead of 44.100 kHz). At most, the difference is less than 0.5%.
Data recorded at 44.100 kHz sample rate and replayed at 44.118 kHz will experience a slight (sub
0.5%) pitch shift as a result of this difference. Note also the USB mode cannot be used to generate a
48kHz samples rate from a 12MHz MCLK. The PLL should be used in this case.
In low sample rate modes (eg. 8kHz voice), the SNR is liable to be degraded if the typical 64fs DAC
clocking rate is used (see Figure 28). In this case, it may be possible to improve the SNR by raising
the DAC clocking rate by setting the DAC_SDMCLK_RATE register field, causing the DAC clocking
rate to be set equal to SYSCLK/4. The DAC_CLKDIV field must still be set as described above to
derive the correct clock for the DAC DSP. In 8kHz voice applications, in systems where SYSCLK >
256fs (or 272fs when applicable), setting DAC_SDMCLK_RATE will result in the SNR performance
being improved. Note that setting DAC_SDMCLK_RATE will result in an increase in power
consumption.
Table 57 DAC Sample Rate Control
R7 (07h)
R10 (0Ah)
REGISTER
ADDRESS
4:2
12
10
BIT
DAC_CLKDIV
[2:0]
DAC_SDMCLK
_RATE
AIF_LRCLKRATE
LABEL
DEFAULT
000b
0b
0b
DAC Sample Rate Divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2.0
011 = SYSCLK / 3.0
100 = SYSCLK / 4.0
101 = SYSCLK / 5.5
110 = SYSCLK / 6.0
111= Reserved
DAC clocking rate
0 = Normal operation (64fs)
1 = SYSCLK/4
LRCLK Rate
0 = Normal mode (256 * fs)
1 = USB mode (272 * fs)
DESCRIPTION
PP, May 2008, Rev 3.1
Pre-Production
106