MAX5100 Maxim, MAX5100 Datasheet
MAX5100
Manufacturer Part Number
MAX5100
Description
+2.7V to +5.5V / Low-Power / Quad / Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
Manufacturer
Maxim
Datasheet
1.MAX5100.pdf
(8 pages)
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The MAX5100 parallel-input, voltage-output, quad 8-bit
digital-to-analog converter (DAC) operates from a sin-
gle +2.7V to +5.5V supply and comes in a space-sav-
ing 20-pin TSSOP package. Internal precision buffers
swing Rail-to-Rail
includes both ground and the positive rail. All four
DACs share a common reference input.
The MAX5100 provides double-buffered logic inputs:
four 8-bit buffer registers followed by four 8-bit DAC
registers. This keeps the DAC outputs from changing
during the write operation. An asynchronous control
pin, LDAC, allows for simultaneous updating of the
DAC registers.
The MAX5100 features a shutdown mode that reduces
current to 1nA, as well as a power-on reset mode that
resets all registers to code 00 hex on power-up.
19-1557; Rev 0; 10/99
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Digital Gain and Offset Adjustments
Programmable Attenuators
Portable Instruments
Power-Amp Bias Control
8-Bit DAC with Rail-to-Rail Voltage Outputs
+2.7V to +5.5V, Low-Power, Quad, Parallel
________________________________________________________________ Maxim Integrated Products
®
, and the reference input range
General Description
Applications
o +2.7V to +5.5V Single-Supply Operation
o Ultra-Low Supply Current
o Ultra-Small 20-Pin TSSOP Package
o Ground to V
o Output Buffer Amplifiers Swing Rail-to-Rail
o Double-Buffered Registers for Synchronous
o Power-On Reset Sets All Registers to Zero
MAX5100AEUP
MAX5100BEUP
Updating
TOP VIEW
0.4mA while Operating
1nA in Shutdown Mode
PART
SHDN
OUTB
OUTA
V
REF
WR
DD
D7
D6
D5
D4
DD
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
10
Reference Input Range
1
2
3
4
5
6
7
8
9
Ordering Information
MAX5100
TSSOP
Pin Configuration
20 TSSOP
20 TSSOP
PIN-PACKAGE
20
19
18
17
16
15
14
13
12
11
OUTC
OUTD
GND
A0
A1
LDAC
D0
D1
D2
D3
Features
(LSB)
INL
±1
±2
1
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