MAX555 Maxim, MAX555 Datasheet - Page 7

• Manufacturer Part Number: MAX555
• Description: 300Msps / 12-Bit DAC with Complementary Voltage Outputs
• Manufacturer: Maxim

The MAX555 features a differential ECL clock input with
selective transparent operation (BYPASS = 1). It is possi-
ble to drive the MAX555 clock single-ended if desired by
tying the CLK input to an external voltage of -1.3V (ECL
V
noise immunity and improved dynamic performance.
In the clocked mode (BYPASS = 0), when the clock line
is low, the slave register is locked out and information
on the digital inputs is permitted to enter the master
register. The clock transition from low to high locks the
master register in its present state and ignores further
changes on the digital inputs. This transition simultane-
ously transfers the contents of the master register to the
slave register, causing the DAC output to change.
Figure 2’s timing diagram illustrates the importance of
operating the MAX555 in the clocked mode. In the trans-
parent mode (BYPASS = 1), both the master and slave
registers are transparent, and changes in input data rip-
Table 1. Output Coding
Figure 2. Timing Diagram
BB
DIGITAL CODE
000000000000
000000000001
011111111111
100000000000
111111111111
). However, using a differential clock provides greater
(D11–D0)
D0
VOUT
VOUT
D11
t
PD2
_______________________________________________________________________________________
TRANSPARENT MODE
BYPASS = 1
t
DD
-0.999756
-0.999512
-0.500000
-0.499756
t
PD1
VOUT
(V)
0
Timing Information
Complementary Voltage Outputs
15
16
16
-0.000244
-0.499756
-0.500000
-0.999756
1
VOUT
(V)
F.S.
F.S.
0
300Msps, 12-Bit DAC with
ple directly to the output. Because the four MSBs are
decoded into 15 identical currents, there is a decode
delay for these bits that is longer than for the eight LSBs.
For the full-scale transition case shown, an intermediate
output of 1/16 full-scale occurs until the four MSBs are
properly decoded. This decode delay seriously degrades
the device’s spurious performance. In addition, skew in
the timing of the input data also directly appears at the
DAC output, further degrading high-speed performance.
MAX555 operation in the clocked mode (BYPASS = 0)
with a differential clock precludes both of these poten-
tial problems and is required for high-speed operation.
Since input data can only enter the master register
when the clock is low (while the slave register is locked
out), data-bus timing skew and the internal MSB
decode delay will not appear at the DAC output. The
DAC currents are switched only when the clock transi-
tions from low to high, after the internal data stabilizes.
The MAX555 has separate pins for analog and digital
supplies. AV
through the substrate of the IC. These potentials
should be derived from the same supply to minimize
voltage mismatch, which would cause substrate current
flow and possible latchup. Appropriate decoupling is
needed to prevent digital-section current spikes from
affecting the analog section (Figure 4).
It is recommended that a multilayer PC board be used,
containing a solid ground and power planes. All analog
D0
VOUT
VOUT
D11
CLK
t
SU
EE
CLOCKED MODE
BYPASS = 0
and DV
Layout and Power Supplies
EE
t
PD3
are connected to each other
t
HOLD
7