MAX555 Maxim, MAX555 Datasheet - Page 8

• Manufacturer Part Number: MAX555
• Description: 300Msps / 12-Bit DAC with Complementary Voltage Outputs
• Manufacturer: Maxim

300Msps, 12-Bit DAC with
Complementary Voltage Outputs
and digital ground pins must be connected directly to
the analog ground plane at the MAX555, preferably with
a “star connection” at the LGND pins (15 and 16).
High-speed ECL inputs, as well as the output from the
MAX555, should employ good transmission-line tech-
niques, with terminations close to the device pins.
Separate power-supply buses for analog and digital
power supplies are recommended as good general
practice. Best results will be achieved by bypassing
the device pins with high-quality ceramic chip capaci-
tors connected physically close to the pins.
The MAX555 uses an internal op-amp circuit to buffer the
reference current. The input to the op amp may be driv-
en with a 1.25mA external current source or a 1V external
voltage reference. The reference input is the VREF pin.
The input impedance to the op amp is 800Ω. As shown
in Figure 1, VREF/2 is brought out externally with 400Ω of
impedance to the op amp. These reference inputs can
be used to vary the full-scale output for high-speed multi-
plying applications. R
log ground. In addition, a 0.1µF capacitor should be
connected from VREF/2 to analog ground to reduce refer-
ence current noise.
The analog outputs are laser trimmed to 50Ω. They can
be used either as a voltage drive with 50Ω impedance, or
to drive into a virtual null using a transimpedance amplifi-
er. Greater speed is achieved driving into 50Ω loads.
The differential outputs of the MAX555 may be used to
drive a balun for conversion to a single-ended output,
while at the same time greatly reducing the second-har-
monic content of the output.
The Typical Operating Characteristics graphs show the
MAX555’s performance when used in direct digital synthe-
sis (DDS) applications for generating RF sine waves. The
first six graphs show the MAX555’s spurious-free dynam-
ic range (SFDR) for clock frequencies of 50MHz to
300MHz at various output frequencies. The seventh
graph shows the SFDR for clock frequencies from
50MHz to 350MHz while producing an output frequen-
cy of about 1/16 the clock frequency.
The last two graphs show the MAX555’s third and sec-
ond harmonic distortion while producing an output fre-
quency of about 1/5 f
100MHz to 300MHz as a function of the reference volt-
age. The third harmonic content of the output can be
reduced at clock frequencies below about 200MHz by
8
__________Applications Information
_______________________________________________________________________________________
OFFSET
CLK
Dynamic Performance
for clock frequencies from
must be connected to ana-
Reference Input
Outputs
reducing the reference voltage from its 1.000V nominal
value. At clock frequencies above about 200MHz, the
output’s third harmonic content is dominated by cou-
pling from the high-speed digital inputs to the output.
Reducing the reference voltage at these high clock
rates actually increases the third harmonic distortion in
the output, since the carrier amplitude drops but the
third harmonic level remains relatively constant.
The second harmonic distortion of the outputs is shown
as a function of clock frequency and reference voltage.
It is relatively constant for clock frequencies below
about 200MHz at different V
third harmonic distortion, however, the second harmon-
ic distortion also increases at clock frequencies over
200MHz for lower V
by bypassing the MAX555 heatspreader (pins 26 and
44) to V
Reducing the swing of the input logic levels and/or
decreasing the rise time of the digital signals can also
improve the output’s harmonic content. Combining
these techniques achieves the best results. Some
experimentation may be required to optimize the
MAX555’s performance for a particular application.
Figure 3 shows the spectrum analyzer plots of the
MAX555 when used in DDS applications. These plots
show the MAX555’s output spectrum at clock frequen-
cies from 50MHz to 300MHz while producing various
output frequencies. Observing the output spectrum
while adjusting the reference voltage or varying the
logic levels is a sensitive method of optimizing MAX555
performance. The plots shown were obtained with a
+0.75V reference voltage with 500mV ECL logic
swings.
Figure 4 shows a typical connection. With VOUT used
to drive a 50Ω line, the unused complementary output,
VOUT, should also be terminated to 50Ω. A 1V refer-
ence voltage at VREF gives a -0.5V full-scale voltage at
VOUT (when doubly terminated with 50Ω on the out-
put). Because some loads may represent a complex
impedance, be sure to match the output impedance
with the load. Mismatching the impedances can cause
reflections that will affect AC-performance parameters.
In all applications, the LOOPCRNT pin is always con-
nected to AGND, and compensation capacitors are
connected to pins ALTCOMPC, ALTCOMPIB, and
LBIAS. The LBIAS compensation is recommended for
non-multiplying applications. AC grounding the heat
spreader on the package (with pins 26 and 44)
reduces digital noise feedthrough and improves the
MAX555’s spurious performance at high data rates.
EE
with a good-quality RF chip capacitor.
REF
values. Minimize these effects
REF
Typical Application
values. As with the