AT91M55800A ATMEL Corporation, AT91M55800A Datasheet

AT91M55800A

Manufacturer Part Number

AT91M55800A

Description

The AT91M55800A Features 8K Bytes of On-chip SRAM, an External Bus Interface, a 6-channel Timer/Counter, 3 Usarts, a Master/slave Spi Interface, a Watchdog Timer, an 8-channel 10-bit ADC, a 2-channel 10-bit DAC, a Clock Generator, Real-time Clock And

Manufacturer

ATMEL Corporation

Datasheet

1.AT91M55800A.pdf (5 pages)

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Errata Sheet V1.0

This Errata Sheet refers to:

•

Internal Product

Reference 56515B

The following datasheets:

AT91M55800A Summary, Rev. 1745AS–07/01

AT91M55800A, Rev. 1745A–07/01

AT91M55800A, Electrical Characteristics Rev. 1776A–07/01

176-lead TQFP and 176-ball BGA devices with the following markings:

When the NWAIT signal is asserted during an external memory access, the fol-

lowing EBI behavior is correct:

–

In these cases, the access is delayed as required by NWAIT and the access oper-

ations are correctly performed.

In other cases, the following erroneous behavior occurs:

–

At maximum speed, asserting the NWAIT in the first access cycle is not possible,

as the sum of the timings “MCKI Falling to Chip Select” and “NWAIT setup to

MCKI rising” are generally higher than one half of a clock period. This leads to

using at least one standard wait state. However, this is not sufficient except to per-

form byte or half-word read accesses. Word and write accesses require at least

two standard wait states.

Warning: Additional NWAIT Constraints

NWAIT is asserted before the first rising edge of the master clock and

respects the NWAIT to MCKI rising setup timing as defined in the Electrical

Characteristics datasheet.

NWAIT is sampled inactive and at least one standard wait state remains to

be executed, even if NWAIT does not meet the NWAIT to first MCKI rising

setup timing (i.e., NWAIT is asserted only on the second rising edge of

MCKI).

32-bit read accesses are not managed correctly and the first 16-bit data

sampling takes into account only the standard wait states. 16- and 8-bit

accesses are not affected.

During write accesses of any type, the NWE rises on the rising edge of the

last cycle as defined by the programmed number of wait states. However,

NWAIT assertion does affect the length of the total access. Only the NWE

pulse length is inaccurate.

AT91M55800A-33AI

AT91M55800A-33CI

AT91

ARM

Microcontrollers

AT91M55800A

Errata Sheet

V1.0

Thumb

Rev. 1780B–01/02

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