AT91M55800A ATMEL Corporation, AT91M55800A Datasheet - Page 3

• Manufacturer Part Number: AT91M55800A
• Description: The AT91M55800A Features 8K Bytes of On-chip SRAM, an External Bus Interface, a 6-channel Timer/Counter, 3 Usarts, a Master/slave Spi Interface, a Watchdog Timer, an 8-channel 10-bit ADC, a 2-channel 10-bit DAC, a Clock Generator, Real-time Clock And
• Manufacturer: ATMEL Corporation

Figure 3. Number of Standard Wait States is One
Note:
Figure 4. Description of the Number of Standard Wait States
1780B–01/02
If the first two conditions are not met during a 32-bit read access, the first 16-bit data is read at the end of the standard
16-bit read access. In the following example, the number of standard waits is one. NWAIT assertions do affect both
NRD pulse lengths, but first data sampling is not delayed. The second data sampling is correct.
If the first two conditions are not met during write accesses, the NWE signal is not affected by the NWAIT assertion.
The following example illustrates the number of standard wait states. NWAIT is not asserted during the first cycle, but
is asserted at the second and last cycle of the standard access. The access is correctly delayed as the NCS line rises
accordingly to the NWAIT assertion. However, the NWE signal waveform is unchanged, and rises too early.
MCKI
NWAIT
NRD
1. These numbers refer to the standard access cycles.
MCKI
NWAIT
NCS
NWE
1 (1)
Access Length = One Wait State + Assertion of the NWAIT for One More Cycle
EB16
32-bit Access = Two 16-bit Accesses
Each Access Length = One Wait State + Assertion for One More Cycle
2 (1)
First Data Sampling
(Erroneous)
EB16
2 (1)
1 (1)
AT91M55800A Errata Sheet
2 (1)
Erroneous NWE Rising
2 (1)
Second Data
Sampling
(Correct)
3