HY27UF161G2M Hynix Semiconductor, HY27UF161G2M Datasheet

HY27UF161G2M

Manufacturer Part Number

HY27UF161G2M

Description

1gbit (128mx8bit / 64mx16bit) NAND Flash Memory

Manufacturer

Hynix Semiconductor

Datasheet

1.HY27UF161G2M.pdf (48 pages)

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Document Title

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory

Revision History

Rev 0.7 / Apr. 2005

Revision

No.

0.0

0.1

0.2

0.3

0.4

1) Initial Draft.

1) Correct Fig.10 Sequential out cycle after read

2) Add the text to Fig.1, Table.1, Table.2

3) Delete ‘3.2 Page program NOTE 1.

4) Change the text ( page 10,13, 45)

5) Add 5.3 Addressing for program operation & Fig.34

1) Change TSOP, WSOP, FBGA package dimension & figures.

2) Correct TSOP, WSOP Pin configurations.

3) Edit figure 15,19 & table 4

4) Add Bad Block Management

5) Change Device Identifier 3rd Byte

1) Add Errata

2) LOCKPRE is changed to PRE.

3) Add Note.4 (table.14)

4) Block Lock Mechanism is deleted.

- Texts, Table, figures are deleted.

5) Add Application Note(Power-On/Off Sequence & Auto Sleep mode.)

- Texts & Figures are added.

6) Edit the figures. (#10~25)

1) Change AC characteristics(tREH)

2) Edit Note.1 (page. 21)

3) Edit the Application note 1,2

4) Edit The Address cycle map (x8, x16)

Relaxed value

Specification

- 3rd Byte ID is changed. (reserved -> don't care)

- 3rd Byte ID table is deleted.

- Texts, Table, Figures are changed.

- text : IO15 - IO8 (x16 only)

- Note : if possible it is better to remove this constrain

- 2.2 Address Input : 28 Addresses -> 27 Addresses

- 3.7 Reset : Fig.29 -> Fig.30

- 5.1 Automatic page read after power up : Fig.30 -> Fig.29

- Change TSOP, WSOP, FBGA package mechanical data

- Change FBGA thickness (1.2 -> 1.0 mm)

- 38th NC pin has been changed Lockpre(figure 3,4)

before: 20ns -> after: 30ns

tCLS

tCLH

tWP

History

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash

tALS

tALH

tDS

tWC

HY27UF(08/16)1G2M Series

HY27SF(08/16)1G2M Series

Draft Date

Nov.29 2004

Jan.19 2005

Aug. 2004

Sep. 2004

Oct. 2004

Preliminary

Remark

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