ADC1005 National Semiconductor Corporation, ADC1005 Datasheet - Page 9

• Manufacturer Part Number: ADC1005
• Description: ADC1005 - 10-Bit Microprocessor Compatible A/D Converter, Package: Cerdip, Pin Nb=20
• Manufacturer: National Semiconductor Corporation

Functional Description
change in the common-mode voltage during this short time
interval can cause conversion errors. For a sinusoidal
common-mode signal, this error is:
where f
V
quency at the CLK IN pin.
For a 60 Hz common-mode signal to generate a
(1.2 mV) with the converter running at 1.8 MHz, its peak
value would have to be 1.46V. A common-mode signal this
large is much greater than that generally found in data
aquisition systems.
3.2 Input Current
Due to the sampling nature of the analog inputs, short dura-
tion spikes of current enter the “+” input and exit the “−” input
at the clock rising edges during the conversion. These cur-
rents decay rapidly and do not cause errors as the internal
comparator is strobed at the end of a clock period.
3.3 Input Bypass Capacitors
Bypass capacitors at the inputs will average the current
spikes noted in 3.2 and cause a DC current to flow through
the output resistances of the analog signal sources. This
charge pumping action is worse for continuous conversions
with the V
conversions with a 1.8 MHz clock frequency with the V
input at 5V, this DC current is at a maximum of approxi-
mately 5 µA. Therefore, bypass capacitors should not be
used at the analog inputs or the V
sources (
for noise filtering and high source resistance is desirable to
minimize capacitor size, the detrimental effects of the volt-
age drop across this input resistance, which is due to the
average value of the input current, can be eliminated with a
full-scale adjustment while the given source resistor and
input bypass capacitor are both in place. This is possible
because the average value of the input current is a linear
function of the differential input voltage.
3.4 Input Source Resistance
Large values of source resistance where an input bypass
capacitor is not used, will not cause errors if the input cur-
rents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series
resistor ( 1 k ) for a passive RC section or add an op amp
RC active low pass filter. For low source resistance applica-
tions ( 0.1 k ) a 4700 pF bypass capacitor at the inputs will
prevent pickup due to series lead induction of a long wire. A
100
both the R and the C are placed outside the feedback loop –
from the output of an op amp, if used.
3.5 Noise
The leads to the analog inputs (pins 6 and 7) should be kept
as short as possible to minimize input noise coupling. Both
noise and undesired digital clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 1 k . Larger values
of source resistance can cause undesired system noise
PEAK
series resistor can be used to isolate this capacitor –
is its peak voltage value and f
CM
>
IN
1 k ). If input bypass capacitors are necessary
is the frequency of the common-mode signal,
(+) input voltage at full scale. For continuous
REF
pin for high resistance
CLK
(Continued)
is the clock fre-
1
⁄
4
LSB error
IN
(+)
9
pickup. Input bypass capacitors, placed from the analog
inputs to ground, can reduce system noise pickup but can
create analog scale errors. See section 3.2, 3.3, and 3.4 if
input filtering is to be used.
4.0 OFFSET AND REFERENCE ADJUSTMENT
4.1 Zero Offset
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V(−) input and applying a small magnitude
positive voltage to the V(+) input. Zero error is the difference
between the actual DC input voltage that is necessary to just
cause an output digital code transition from 00 0000 0000 to
00 0000 0001 and the ideal
for V
The zero of the A/D normally does not require adjustment.
However, for cases where V
reduced span applications (V
may be desired. The converter can be made to output an all
zero digital code for an arbitrary input by biasing the A/D’s
V
operation of the A/D.
4.2 Full Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage that is 1
analog full-scale voltage range and then adjusting the mag-
nitude of the V
changing from 11 1111 1110 to 11 1111 1111.
4.3 Adjusting for an Arbitrary Analog
Input Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
that does not go to ground), this new zero reference should
be properly adjusted first. A V
desired zero reference plus
culated for the desired analog span, 1 LSB = analog span/
1024) is applied to selected “+” input and the zero reference
voltage at the corresponding “−” input should then be ad-
justed to just obtain the 000
The full-scale adjustment should be made [with the proper
V
input given by:
where V
V
(Both are ground referenced).
The V
change from 3FF
ment procedure.
For an example see the Zero-Shift and Span-Adjust circuit
below.
5.0 POWER SUPPLIES
Noise spikes on the V
errors as the comparator will respond to this noise. A low
inductance tantalum filter capacitor should be used close to
the converter V
recommended. If an unregulated voltage is available in the
IN
IN
MIN
(−) input at that voltage. This utilizes the differential input
(−) voltage applied] by forcing a voltage to the V
REF
= the low end (the offset zero) of the analog range.
REF
MAX
= 5.0 V
(or V
= the high end of the analog input range and
REF
CC
CC
DC
HEX
) voltage is then adjusted to provide a code
input for a digital output code that is just
).
pin and values of 1 µF or greater are
to 3FE
CC
supply line can cause conversion
1
HEX
HEX
⁄
1
REF
1
2
⁄
⁄
2
2
LSB value (
IN(MIN)
IN
LSB down from the desired
LSB (where the LSB is cal-
. This completes the adjust-
(+) voltage that equals this
001
<
5V), an offset adjustment
HEX
is not ground and in
code transition.
1
⁄
2
LSB = 2.45 mV
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IN
(+)