ADC4320 Analogic Corporation, ADC4320 Datasheet - Page 6

• Manufacturer Part Number: ADC4320
• Manufacturer: Analogic Corporation

Figure 14. Offset and Gain Adjustment Circuit.
* denotes a 0/1 or 1/0 transition
Figure 15. Coding and Trim Calibration Table.
Figure 16. Timing Diagram.
Figure 17. ADC432X Series Mechanical Diagram.
UNIPOLAR BINARY
+FS
1/2 FS 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = +5.00000V
Offset
OFFSET BINARY
+FS
Offset
–FS
2’S COMPLEMENT
+FS
Offset
–FS
Time (ns)
S/H Cont
(Internal)
A/D Clock
(Internal)
Transfer
Trigger
Data
1.3"
33.02 mm
(on center)
MSB
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * = +9.99977V
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * = +0.00000V
MSB
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * = +2.49989V +4.99977V
* * * * * * * * * * * * * * = –0.00004V –0.00008V
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * = –2.49996V –4.99992V
MSB
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * = +2.49989V +4.99977V
* * * * * * * * * * * * * * = –0.00004V –0.00008V
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * = –2.49996V –4.99992V
0.225 Max.
0
N
0.225 Min.
46
Gain Adj.
+5V REF
–5V REF
Off Adj.
N-1 Data
Hold
Gnd.
ADC4325
ADC4320
ADC4322
0.100" (2.54 mm) Typ. (on center)
Note: If not used,
connect Pins 13, 14, and 15
C 1
Top View
2.4" (60.96 mm)
LSB
LSB
LSB
1.1 µs
620ns
300 ns
C 2
Sample
R 1
R 2
0V TO +10V
±2.5V Input
±2.5V Input
1.3 µs
750ns
400 ns
0.018 (0.45 mm) Dia. Typ.
R 1 = 50K
R 2 = 50K
C 1 = 0.1 µF
C 2 = 0.1 µF
25 ns Min.
N Data
2.0 µs
1.0µs
500 ns
N + 1
23
24
±5V Input
±5V Input
(33 mm)
1.300
(40.64 mm)
1.6
To check the trim procedure, apply 1/2 full scale volt-
age for a unipolar range or –full scale voltage for the
bipolar ranges and check that the digital code is ±1
LSB of the stated code.
PRINCIPLE OF OPERATION
The ADC432X Series converters are 16-bit sampling
A/D converters with throughput rates of up to 2 MHz.
These converters are available in three externally con-
figured full scale ranges of 5V p-p, 10V p-p and 20V p-p.
Options are externally or user-programmable for bipolar
and unipolar inputs of ±2.5V, ±5V, ±10V and 0 to +10V.
Two’s complement format can be obtained by utilizing
B1 instead of B1.
* DNC– Do Not Connect
Figure 18. Pin Assignment.
Figure 19. Operating Principle.
S/H In 1
S/H In 2
S/H In 3
DAC In
From
Logic
S/H In 1
S/H In 2
S/H In 3
9
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A= -1 or -2
S/H Amp
16-Bit
Linear
DAC
A= -1 or -2
S/H Amp
ANA RTN
+15V
–15V
S/H IN 1
S/H IN 2
S/H IN 3
SIG RTN
DNC*
ANA RTN
+15V
–15V
DNC
EXT OFFSET ADJ
ANA RTN
EXT GAIN ADJ
+REF OUT
–REF OUT
ANA RTN
TRIGGER
DIG RTN
DIG RTN
HI BYTE EN
LO BYTE EN
10V p-p
10V p-p
+
–
A= –6.4
1st Pass
+
–
2nd Pass
A= -0.2
+
–
A= –4
2V p-p
10-Bit
(2nd Pass)
ADC
To DAC
0.5V p-p
PIN#
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
10-Bit
ADC
9
9
+5V
DIG RTN
O/U FLOW
BIT 1N
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
BIT 16
TRANSFER
+5V
DIG RTN
9
Logic
Logic
16
O/U Flow
B1-B16
B1
Transfer