ADC4320 Analogic Corporation, ADC4320 Datasheet - Page 7

• Manufacturer Part Number: ADC4320
• Manufacturer: Analogic Corporation

To understand the operating principles of the A/D con-
verters, refer to the timing diagram of Figure 16 and
the simplified block diagram of Figure 19. The simpli-
fied block diagram illustrates the two successive pass-
es in the sub-ranging scheme of the converters.
The A/D converter is factory-trimmed and optimized to
operate with a 10V p-p input voltage range. Scaling re-
sistors at the S/H inputs configure the three input
ranges and provide a S/H output voltage to the A/D
converter of 10V p-p.
The first pass starts with a high-to-low transition of the
trigger pulse. This signal places the S/H into the Hold
mode and starts the timing logic. The path of the 10V
p-p input signal during the first pass is through a 5:1 at-
tenuator circuit to the 10-bit ADC with an input range of
2V p-p. At 35 ns, the ADC converts the signal and the
9 bits are latched both into the logic as the MSBs and
into the 16-bit accurate DAC for the second pass.
The second pass subtracts the S/H output and the 9-
bit, 16-bit accurate DAC output with the result equal to
the 9-bit quantization error of the DAC, or 19.5 mV p-p.
The “error” voltage is then amplified by a gain of 25.6
and is now 0.5V p-p or 1/4 the full scale range of the
ADC, allowing a 2-bit overlap safety margin. When the
DAC and the “error” amplifier have had sufficient time to
settle to 16-bit accuracy, the amplified “error” voltage is
then digitized by the ADC with the 9-bit second pass re-
sult latched into the logic. At this time the S/H returns to
the sample mode to begin acquiring the next sample.
The 1/4 full scale range in the second pass produces a
2-bit overlap of the two passes. This provides an out-
put word that is accurate and linear to 16 bits. This
method corrects for any gain and linearity errors in the
amplifying circuitry, as well as the 10-bit flash A/D con-
verter. Without the use of this overlapping correction
scheme, it would be necessary that all the components
in the converters be accurate to the 16-bit level. While
such a design might be possible to realize on a labora-
tory benchtop, it would be clearly impractical to
achieve on a production basis. The key to the conver-
sion technique used in the converters is the 16-bit ac-
curate and 16-bit linear D/A converter which serves as
the reference element for the conversion’s second
pass. The use of proprietary sub-ranging architecture
in the converters results in a sampling A/D converter
that offers unprecedented speed and transfer charac-
teristics at the 16-bit level.
The converter has a 3-state output structure. Users
can enable the eight MSBs and B1 with HIBYTEN and
the eight LSBs with LOBYTEN (both are active low).
This feature makes it possible to transfer data from the
converter to an 8-bit microprocessor bus. However, to
prevent the coupling of high frequency noise from the
microprocessor bus into the A/D converter, the output
data must be buffered.
Layout Considerations
Because of the high resolution of the A/D converters, it
is necessary to pay careful attention to the printed-cir-
cuit layout for the device. It is, for example, important
to keep analog and digital grounds separate at the
power supplies. Digital grounds are often noisy or
“glitchy,” and these glitches can have adverse effects
on the performance of the converters if they are intro-
duced to the analog portions of the A/D converter’s cir-
cuitry. At 16-bit resolution, the size of the voltage step
between one code transition and the succeeding one
for a 5V full scale range is only 76 µV. It is evident that
any noise in the analog ground return can result in er-
roneous or missing codes. It is important in the design
of the PC board to configure a low-impedance ground-
plane return on the printed-circuit board. It is only at
this point where the analog and digital power returns
should be made common.
The Analogic ADC4322 EB-1 evaluation board has
been designed and laid out for optimum performance
with the converter series. The board layout and
schematic are shown in figures 20-22 as examples of
decoupling and layout techniques.