MAX807N Maxim Integrated Products, MAX807N Datasheet - Page 7

• Manufacturer Part Number: MAX807N
• Description: Full-Featured P Supervisory Circuit with 1.5eset Accuracy
• Manufacturer: Maxim Integrated Products

______________________________________________________________Pin Description
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
LOW LINE
BATT ON
BATT OK
CE OUT
RESET
RESET
NAME
CE IN
WDO
BATT
GND
OUT
PFO
WDI
V
MR
PFI
CC
Full-Featured µP Supervisory Circuit with
_______________________________________________________________________________________
Power-Fail Input. When PFI is less than V
Power-Fail Output. This CMOS-logic output goes low when PFI is less than V
V
Input Supply Voltage, nominally +5V. Bypass with a 0.1µF capacitor to GND.
Watchdog Input. If WDI remains high or low longer than the the watchdog timeout period (1.6sec
typical), WDO goes low. Leave unconnected to disable the watchdog function.
Ground
Manual-Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR remains low
and for 200ms after MR returns high. MR is an active-low input with an internal pull-up to V
driven using TTL or CMOS logic, or shorted to ground with a switch. Connect to V
nected if not used.
Low-Line Comparator Output. This CMOS-logic output goes low when V
threshold. Use this output to generate an NMI to initiate an orderly shutdown routine when V
LOW LINE swings between V
Active-High Reset Output. RESET is the inverse of RESET. It is a CMOS output that sources and sinks
current. RESET swings between V
Active-Low Reset Output. RESET is triggered and stays low when V
when MR is low. It remains low 200ms after V
RESET has a strong pull-down but a relatively weak pull-up, and can be wire-OR connected to logic
gates. Valid for V
Watchdog Output. This CMOS-logic output goes low if WDI remains high or low longer than the watch-
dog timeout period (t
unconnected. WDO is high during reset. WDO swings between V
generate resets during watchdog faults.
Chip-Enable Output. Output to the chip-enable gating circuit. CE OUT is pulled up to the higher of V
or V
Chip-Enable Input
Battery On Output. CMOS-logic output/external bypass switch driver. High when OUT is connected to
BATT and low when OUT is connected to V
transistor to BATT ON for I
V
Backup-Battery Input. When V
BATT. V
BATT is bypassed with a 0.1µF capacitor to GND. If no battery is used, connect BATT to ground, and
connect V
Battery OK Signal Output. High in normal operating mode when V
V
Output Supply Voltage to CMOS RAM. When V
connected to V
OUT with a 0.1µF capacitor to GND.
CC
CC
CC
BATT
≥ 4V. PFO swings between V
and V
≥ 4V.
BATT
, when the chip-enable gate is disabled.
CC
BATT
may exceed V
and OUT together.
CC
, and GND.
CC
. When V
≥ 1V. RESET swings between V
WD
), and remains low until the next transition of WDI. WDO remains high if WDI is
OUT
CC
CC
CC
CC
falls below the reset threshold and V
. The battery can be removed while the MAX807 is powered-up, provided
requirements exceeding 250mA. BATT ON swings between the higher of
and GND.
CC
falls below the reset threshold and V
CC
and GND.
and GND.
PFT
±1.5% Reset Accuracy
CC
(2.265V), PFO goes low. Connect to ground when unused.
CC
. Connect the base of a PNP transistor or gate of a PMOS
FUNCTION
CC
rises above the reset threshold or MR returns high.
exceeds the reset threshold or V
CC
and GND.
CC
BATT
BATT
CC
and GND. Connect WDO to MR to
BATT
is below the reset threshold or
exceeds V
, OUT connects to BATT. Bypass
CC
, OUT switches from V
falls to 52mV above the reset
PFT
(2.265V). Valid for
CC
BOK
CC
, or leave uncon-
> V
(2.265V). Valid for
BATT
CC
CC
. It can be
, OUT is
is falling.
CC
CC
to
7