MAX807N Maxim Integrated Products, MAX807N Datasheet - Page 9

• Manufacturer Part Number: MAX807N
• Description: Full-Featured P Supervisory Circuit with 1.5eset Accuracy
• Manufacturer: Maxim Integrated Products

Figure 2a. Timing Diagram, V
The RESET output is active low and implemented with a
strong pull-down/relatively weak pull-up structure. It is
guaranteed to be a logic low for 0V < V
vided V
tery, RESET is guaranteed valid for V
sinks 3.2mA at 0.1V saturation voltage in its active state.
The RESET output is the inverse of the RESET output; it
both sources and sinks current and cannot be wire-OR
connected.
Many µP-based products require manual-reset capabil-
ity to allow an operator or test technician to initiate a
reset. The Manual Reset (MR) input permits the genera-
tion of a reset in response to a logic low from a switch,
WDO, or external circuitry. Reset remains asserted
while MR is low, and for 200ms after MR returns high.
MR has an internal 50µA to 200µA pull-up current, so it
can be left open if it is not used. MR can be driven with
TTL or CMOS-logic levels, or with open-drain/collector
outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function;
external debounce circuitry is not required. If MR is dri-
ven from long cables or if the device is used in a noisy
environment, connect a 0.1µF capacitor from MR to
ground to provide additional noise immunity. As shown
in Figure 3, diode-ORed connections can be used to
allow manual resets from multiple sources. Figure 4
shows the reset timing.
V
LOW LINE
V
V
V
CE OUT
RESET
RESET
V
CC
BATT
SHOWN FOR V
V
BATT
is greater than 2V. Without a backup bat-
Full-Featured µP Supervisory Circuit with
V
RST
_______________________________________________________________________________________
CC
= 0V to 5V, V
V
LL
CC
BATT
Rising
t
t
Manual Reset Input
RP
RP
= 2.8V, CE IN = GND
CC
CC
≥ 1. It typically
< V
RST
, pro-
Figure 2b. Timing Diagram, V
Figure 3. Diode “OR” connections allow multiple reset sources
to connect to MR.
The watchdog circuit monitors the µP’s activity. If the
µP does not toggle the watchdog input (WDI) within
1.6sec, WDO goes low. The internal 1.6sec timer is
cleared and WDO returns high when reset is asserted
or when a transition (low-to-high or high-to-low) occurs
at WDI while RESET is high. As long as reset is assert-
ed, the timer remains cleared and does not count. As
soon as reset is released, the timer starts counting
(Figure 5). Supply current is typically reduced by 10µA
when WDI is at a valid logic level.
±1.5% Reset Accuracy
V
LOW LINE
V
V
V
CE OUT
SOURCES
RESET
RESET
OTHER
RESET
V
CC
* DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
MANUAL RESET
SHOWN FOR V
V
RST
+ V
LR
CC
= 5V to 0V, V
V
RST
*
*
CC
Falling
BATT
V
BATT
= 2.8V, CE IN = GND
Watchdog Timer
MR
Watchdog Input
MAX807
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