MAX9853 Maxim Integrated Products, MAX9853 Datasheet - Page 62
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MAX9853
Manufacturer Part Number
MAX9853
Description
(MAX9851 / MAX9853) Stereo Audio CODECs
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX9853.pdf
(71 pages)
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A write to the MAX9851/MAX9853 includes transmission
of a START condition, the slave address with the R/W bit
set to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a STOP
condition. Figure 13 illustrates the proper frame format for
writing one byte of data to the MAX9851/MAX9853.
Figure 14 illustrates the frame format for writing n-bytes of
data to the MAX9851/MAX9853.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9851/
MAX9853. The MAX9851/MAX9853 acknowledge
receipt of the address byte during the master-generat-
ed ninth SCL pulse.
The second byte transmitted from the master configures
the MAX9851/MAX9853’s internal register address point-
Stereo Audio CODECs with Microphone, DirectDrive
Headphones, Speaker Amplifiers, or Line Outputs
Figure 13. Writing 1 Byte of Data to the MAX9851/MAX9853
Figure 14. Writing n-Bytes of Data to the MAX9851/MAX9853
62
S
ACKNOWLEDGE FROM MAX9851/
S
______________________________________________________________________________________
ACKNOWLEDGE FROM MAX9851/MAX9853
SLAVE ADDRESS
SLAVE ADDRESS
MAX9853
R/W
0
R/W
A
ACKNOWLEDGE FROM MAX9851/
0
REGISTER ADDRESS
Write Data Format
A
ACKNOWLEDGE FROM MAX9851/MAX9853
MAX9853
REGISTER ADDRESS
A
ACKNOWLEDGE FROM MAX9851/
B7 B6
er. The pointer tells the MAX9851/MAX9853 where to
write the next byte of data. An acknowledge pulse is sent
by the MAX9851/MAX9853 upon receipt of the address
pointer data.
The third byte sent to the MAX9851/MAX9853 contains
the data that will be written to the chosen register. An
acknowledge pulse from the MAX9851/MAX9853 sig-
nals receipt of the data byte. The address pointer auto
increments to the next register address after each
received data byte. This autoincrement feature allows a
master to write to sequential registers within one contin-
uous frame. Figure 14 illustrates how to write to multiple
registers with one frame. The master signals the end of
transmission by issuing a STOP condition.
Register addresses greater than 0x1B are reserved. Do
not write to these addresses.
B5 B4
DATA BYTE 1
1 BYTE
REGISTER ADDRESS POINTER
AUTOINCREMENT INTERNAL
B3 B2
MAX9853
B1 B0
A
B7
ACKNOWLEDGE FROM MAX9851/MAX9853
A
B6
ACKNOWLEDGE FROM MAX9851/
B5
B7 B6
DATA BYTE
B4
1 BYTE
B5 B4
B3
DATA BYTE n
1 BYTE
B2
REGISTER ADDRESS POINTER
B3 B2
AUTOINCREMENT INTERNAL
MAX9853
B1
B1 B0
B0
A
A
P
P