SA07U Apex Microtechnology Corporation, SA07U Datasheet - Page 4

• Manufacturer Part Number: SA07U
• Description: PWM Amplifier
• Manufacturer: Apex Microtechnology Corporation

GENERAL
mounting can be found in the “General Operating Consider-
ations” section of the Apex data book. For information on the
package outline, heatsinks, and mounting hardware see the
“Package Outlines” and “Accessories” section of the data book.
Also see Application Note 30 on “PWM Basics.”
CLOCK CIRCUIT AND RAMP GENERATOR
approximately 1MHZ. The CLK OUT pin will normally be tied
to the CLK IN pin. The clock is divided by two and applied to an
RC network which produces a ramp signal at the RAMP pin. An
external clock signal can be applied to the CLK IN pin for
synchronization purposes. If a clock frequency lower than
1MHz is chosen an external capacitor must be tied to the
RAMP pin. This capacitor, which parallels an internal capaci-
tor, must be selected so that the ramp oscillates 2.5 volts p-p
with the lower peak 1.25 volts above ground.
BYPASSING
proper operation. Failure to do so can cause erratic and low
efficiency operation as well as excessive ringing at the outputs.
The Vs supply should be bypassed with at least a 1 F ceramic
capacitor in parallel with another low ESR capacitor of at least
10 F per amp of output current. Capacitor types rated for
switching applications are the only types that should be consid-
ered. The bypass capacitors must be physically connected
directly to the power supply pins. Even one inch of lead length
will cause excessive ringing at the outputs. This is due to the
very fast switching times and the inductance of the lead
connection. The bypassing requirements of the Vcc supply are
less stringent, but still necessary. A .1 F to .47 F ceramic
capacitor connected directly to the Vcc pin will suffice.
APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: [phone]
SA07
Helpful information about power supplies, heatsinking and
The clock frequency is internally set to a frequency of
Adequate bypassing of the power supplies is required for
6
5
4
3
2
1
0
0
TOTAL VOLTAGE DROP
1
OUTPUT, I (A)
2
85 C
–55 C –25 C
100 C
125 C
3
4
25 C
5
NOISE FILTERING
+PWM connection. A wise precaution is to low pass filter this
connection. Adjust the pass band of the filter to 10 times the
bandwidth required by the application. Keep the resistor value
to 100 ohms or less since this resistor becomes part of the
hysteresis circuit on the pwm comparator.
PCB LAYOUT
in one circuit both high speed high power switching and low
level analog signals. Certain layout rules of thumb must be
considered when a circuit board layout is designed using the
SA07:
1. Bypassing of the power supplies is critical. Capacitors must
2. Make all ground connections with a star pattern at pin 7.
3. Beware of capacitive coupling between output connections
4. Do not run small signal traces between the pins of the output
5. Do not allow high currents to flow into the ground plane.
6. Separate switching and analog grounds and connect the
INTEGRATOR
feedback and also the open loop gain for the overall application
circuit accuracy. Recommended value of C
stability. However, poles and zeroes can be added to the circuit
for overall loop stability as required.
CURRENT LIMIT
SENSE B. The two pins can be shorted in the voltage mode
connection but both must be used in the current mode connec-
tion (see figures A and B). It is recommended that R
resistors be non-inductive. Load current flows in the I SENSE
pins. To avoid errors due to lead lengths connect the I LIMIT/
SHDN pin directly to the R
network and shutdown divider resistor) and connect the R
resistors directly to the GND pin. Do not connect R
resistors to the ground plane.
Switching noise can enter the SA07 through the INT OUT to
The designer needs to appreciate that the SA07 combines
The integrator provides the inverted signal for negative
There are two load current sensing pins, I SENSE A and I
be connected directly to the power supply pins with very
short lead lengths (well under 1 inch). Ceramic chip capaci-
tors are best.
and signal inputs through the parasitic capacitance be-
tween layers in multilayer PCB designs.
section (pins 11-16).
two only at pin 7 as part of the star pattern.
LIMIT
resistors (through the filter
CONSIDERATIONS
INT
OPERATING
is 10 pF for
LIMIT
sense
LIMIT
LIMIT