AD1986 Analog Devices, AD1986 Datasheet - Page 26

• Manufacturer Part Number: AD1986
• Manufacturer: Analog Devices

AD1986
Register
I1
(Sense Cycle
(Read/Write))
I [3:2]
(
(RO))
I4
(Interrupt Status
(Read/Write))
x
POWER-DOWN CTRL/STAT (REGISTER 0x26)
The ready bits are read only; writing to REF, ANL, DAC, and ADC has no effect. These bits indicate the status for the AD1986
subsections. If the bit is 1 then that subsection is ready. ‘Ready’ is defined as the subsection able to perform in its nominal state.
Reg
0x26
Table 46.
Register
ADC (RO)
(ADC Section
Status (RO))
ADC (RO)
((Front DAC
Status (RO))
ANL (RO)
(Analog
Amplifiers,
Attenuators and
Mixers Status
(RO))
Interrupt Cause
Name
Power-
Down
Ctrl/Stat
ADC
0
1
DAC
0
1
ANL
0
1
Function
Writing a 1 to this bit causes a sense cycle start if supported. If a sense cycle is in progress, writing a 0 to this bit will
abort the sense cycle. The data in the sense result register (0x6A, Page 01) may or may not be valid, as determined by
the IV bit.
I1
0
1
These bits will indicate the cause(s) of an interrupt. This information should be used to service the correct interrupting
event(s). If the Interrupt Status (Bit I4) is set, one or both of these bits must be set to indicate the interrupt cause.
Hardware will reset these bits back to zero when the interrupt status bit is cleared.
I2
0
1
I3
0
1
Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt
enable (I0) status. An interrupt in the GPI in Slot 12 in the AC link will follow this bit change when interrupt enable (I0)
is unmasked. If this bit is set, one or both of I3 or I2 must be set to indicate the interrupt cause.
I4
0
1
Reserved.
D15
EAPD
D14
PR6
D13
PR5
ADC Status
ADC not ready
ADC sections ready to transmit data
Front DAC Status
ADC not ready
ADC sections ready to transmit data
Analog Status
Analog amplifiers, attenuators and mixers not ready
Analog amplifiers, attenuators and mixers ready
Read
Sense cycle completed (or not initiated)
Sense cycle still in process
Interrupt Status
Sense status has not changed (did not cause interrupt). Default
Sense cycle completed or new sense information is available
GPIO status change did not cause interrupt
GPIO status change caused interrupt
Read
Interrupt clear
Interrupt generated
D12
PR4
D11
PR3
D10
PR2
Rev. 0 | Page 26 of 52
D9
PR1
D8
PR0
D7
x
x
D6
D5
x
Preliminary Technical Data
Default
Default
D4
x
REF
D3
D2
ANL
Write
Aborts sense cycle (if in
process)
Initiate sense cycle
Write
No operation
Clears interrupt
Default: 0
DAC
D1
D0
ADC
0x000x
Default