AD1986 Analog Devices, AD1986 Datasheet - Page 30

• Manufacturer Part Number: AD1986
• Manufacturer: Analog Devices

AD1986
SURROUND DAC PCM RATE (REGISTER 0x2E)
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit
(0x2A D00) is 0, this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.
If the DRA bit (0x2A D01) is set, the surround DAC is inoperative and automatically powered down.
Reg
0x2E
Table 50.
Register
R [15:0]
(Sample
Rate)
C/LFE DAC PCM RATE (REGISTER 0x30)
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit
(0x2A D00) is 0 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.
If the DRA bit (0x2A D01) is set, the C/LFE DAC is inoperative and automatically powered down.
Reg
0x30
Table 51.
Register
R [15:0]
(Sample
Rate)
ADC PCM RATE (REGISTER 0x32)
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit (0x2A
D00) is 0 (zero) this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.
Reg
0x32
Table 52.
Register
R [15:0]
(Sample
Rate)
Name
SURR_1 DAC PCM
Rate
Name
C/LFE DAC
PCM Rate
Name
ADC 0 PCM
Rate
Function
The sampling frequency range is from 7 kHz (0x01B58) to 48 kHz (0xBB80) in 1 Hz increments. If zero is written to VRA then the
sample rates are reset to 48k.
Function
The sampling frequency range is from 7 kHz (0x01B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to VRA then the
sample rates are reset to 48k.
Function
The sampling frequency range is from 7 kHz (0x01B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to VRA then the
sample rates are reset to 48k.
D15
R15
D15
R15
D15
R15
D14
R14
D14
R14
D14
R14
D13
R13
D13
R13
D13
R13
D12
R12
D12
R12
D12
R12
D11
R11
D11
R11
D11
R11
Rev. 0 | Page 30 of 52
D10
R10
D10
R10
D10
R10
D9
R9
D9
R9
D9
R9
D8
R8
D8
R8
D8
R8
D7
R7
D7
R7
D7
R7
D6
R6
D6
R6
R6
D6
D5
R5
Preliminary Technical Data
D5
R5
D5
R5
D4
R4
D4
R4
D4
R4
D3
R3
D3
R3
D3
R3
D2
R2
D2
R2
D2
R2
D1
R1
D1
R1
D1
R1
D0
R0
D0
R0
D0
R0
Default
0xBB80
0xBB80
0xBB80
Default
Default