ADSP-2183 Analog Devices, ADSP-2183 Datasheet - Page 14

• Manufacturer Part Number: ADSP-2183
• Description: DSP Microcomputer
• Manufacturer: Analog Devices

ADSP-2183
Parameter
Clock Signals and Reset
Timing Requirements:
t
t
t
Switching Characteristics:
t
t
t
Control Signals
Timing Requirement:
t
NOTE
1
Parameter
Interrupts and Flag
Timing Requirements:
t
t
Switching Characteristics:
t
t
NOTES
1
2
3
4
5
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
If IRQx and FI inputs meet t
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
CKI
CKIL
CKIH
CKL
CKH
CKOH
RSP
oscillator start-up time).
IFS
IFH
FOH
FOD
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
RESET Width Low
IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High
Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low
IFS
CLKOUT
and t
CLKIN
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
OUTPUTS
CLKOUT
FLAG
IRQx
PFx
FI
t
CKIL
5
t
CKI
5
t
t
FOH
FOD
t
CKL
1, 2, 3, 4
1, 2, 3, 4
t
IFH
Min
38
15
15
0.5t
0.5t
0
5t
t
CK
CKOH
t
Min
0.25t
0.25t
0.5t
CKH
CK
CK
t
1
IFS
– 7
– 7
CK
t
CKIH
CK
CK
– 7
+ 15
Max
0.5t
Max
100
20
CK
+ 6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit