ADSP-2183 Analog Devices, ADSP-2183 Datasheet - Page 15

• Manufacturer Part Number: ADSP-2183
• Description: DSP Microcomputer
• Manufacturer: Analog Devices

Parameter
Bus Request–Bus Grant
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
2
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to xMS,
RD, WR Disable
xMS, RD, WR
Disable to BG Low
BG High to xMS,
RD, WR Enable
xMS, RD, WR
Enable to CLKOUT High
xMS, RD, WR
Disable to BGH Low
BGH High to xMS,
RD, WR Enable
PMS, DMS
CLKOUT
BMS, RD
CLKOUT
BGH
BR
BG
WR
2
2
t
SD
t
1
BH
1
t
t
BS
t
SDBH
SDB
Min
0.25t
0.25t
0
0
0.25t
0
0
CK
CK
CK
+ 2
+ 17
– 4
t
SE
t
SEC
t
SEH
Max
0.25t
CK
ADSP-2183
+ 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns