ADSP-BF531 Analog Devices, ADSP-BF531 Datasheet - Page 16

• Manufacturer Part Number: ADSP-BF531
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices

ADSP-BF531/ADSP-BF532/ADSP-BF533
PIN DESCRIPTIONS
ADSP-BF531/2/3 processor pin definitions are listed in
All pins are three-stated during and immediately after reset,
except the Memory Interface, Asynchronous Memory Control,
and Synchronous Memory Control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pullups or pulldowns as noted in
the table footnotes.
Table 9. Pin Descriptions
Pin Name
Memory Interface
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
Asynchronous Memory Control
AMS3–0
ARDY
AOE
ARE
AWE
Synchronous Memory Control
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Timers
TMR0
TMR1/PPI_FS1
TMR2/PPI_FS2
3
I/O Function
O
I/O Data Bus for Async/Sync Access
O
I
O
O
O
I
O
O
O
O
O
O
O
O
O
O
I/O Timer 0
I/O Timer 1/PPI Frame Sync1
I/O Timer 2/PPI Frame Sync2
Address Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access
Bus Request
Bus Grant
Bus Grant Hang
Bank Select
Hardware Ready Control
Output Enable
Read Enable
Write Enable
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output
A10 Pin
Bank Select
Rev. 0 | Page 16 of 56 | March 2004
Table
9.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Driver Type
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
C
C
C
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
5
5
5
1