ADSP-BF531 Analog Devices, ADSP-BF531 Datasheet - Page 38

• Manufacturer Part Number: ADSP-BF531
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices

ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test And Emulation Port Timing
Table 31
Table 31. JTAG Port Timing
1
2
3
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs=DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
50 MHz maximum
System Outputs=DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
RESET, NMI, BMODE1–0, BR, PP3–0.
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
and
TCK
TMS
TDO
SYSTEM
OUTPUTS
Figure 24
INPUTS
TDI
SYSTEM
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
describe JTAG port operations.
2
(Measured in TCK cycles)
t
DSYS
t
DTDO
t
SSYS
t
STAP
Rev. 0 | Page 38 of 56 | March 2004
1
t
TCK
3
1
Figure 24. JTAG Port Timing
t
HSYS
t
HTAP
Min
20
4
4
5
4
0
4
Max
10
12
Unit
ns
ns
ns
ns
ns
TCK
ns
ns