ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 27

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

7
8
9
10
11
12
REV. A
For additional requirement details, see
TCK_FE indicates TCK falling edge.
These pins may change only during reset; recommend connecting it to V
Reference clock depends on function.
System inputs are: IRQ3–0, BMS, LCLKRAT2–0, SCLKFREQ, BM, TMR0E, FLAG3–0, ID2–0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE,
System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3–0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1–0, HDQM, LDQM, MSSD,
CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7–0, L0CLKIN, L0DAT7–0, L1CLKIN, L1DAT7–0, L2CLKIN,
L2DAT7–0, L2DIR, L3CLKIN, L3DAT7–0, DS2–0, CONTROLIMP2–0, RESET, DMAR3–0.
SDCKE, SDWE, CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, ACK, BR7–0, L0CLKOUT, L0DAT7–0, L0DIR, L1CLKOUT, L1DAT7–0,
L1DIR, L2CLKOUT, L2DAT7–0, L2DIR, L3CLKOUT, L3DAT7–0, L3DIR, EMU.
ASYNCHRONOUS
THREE-STATE
REFERENCE
INPUT OR
OUTPUT
OUTPUT
SIGNAL
SIGNAL
SIGNAL
CLOCK
INPUT
Reset and Booting on Page
Figure 9. General AC Parameters Timing
OUTPUT
VALID
1.5V
DISABLE
OUTPUT
1.5V
1.5V
8.
DD_IO
–27–
1.5V
/V
SS
PULSEWIDTH
.
SETUP
INPUT
OUTPUT
OUTPUT
ENABLE
INPUT
HOLD
HOLD
ADSP-TS101S